Virtex-6

This overview outlines the features and product selection of the Virtex®-6 family.

This data sheet contains the DC and switching characteristic specifications for the Virtex®-6 family.

All package files are ASCII files in txt format.

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

This guide describes the GTH transceivers available in all Virtex®-6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package.

This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the System Monitor functionality.

This guide provides information on PCB design for Virtex@reg;-6 devices, with a focus on strategies for making design decisions at the PCB and the interface level.

Errata for the Virtex®-6 LX240T, LX195T, and LX130T devices.

This application note describes a system using the Virtex®-6 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-6 ML605 development board.

Targeted design platforms are simpler, smarter, and more strategically viable design platforms that offer customers the optimum in flexibility, accessibility, applicability, and time to market.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

The FPGA Mezzanine Card (FMC) standard, developed by a consortium of companies ranging from FPGA vendors to end users, specifically targets FPGAs, increasing I/O flexibility and lowering costs in a broad range of applications.

FPGAs enabled with serial I/O offer the ideal balance of bandwidth, density, performance, flexibility, and cost for SoC designs. Xilinx offers a portfolio of serial I/O technology that addresses the full spectrum of bandwidth requirements for products ranging from commercial video displays to broadcast video ultra-high bandwidth wired telecommunications systems.

The Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation Kit for Synopsys HSPICE enables signal integrity simulations of a communication link between Virtex-6 FPGA GTX transceivers. This kit includes models of the line driver of the transmitter and the analog front end of the receiver of the GTX transceivers.