Virtex-E EM

All package files are ASCII files in zip format.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that the Xilinx discontinuation of certain Virtex® (Virtex-E, Virtex-EM, Virtex-II and EasyPath™ Virtex-II families) and Spartan® (Spartan-IIE family) FPGA products has been retracted due to a two year extension of production capability.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

This application note describes in-circuit partial reconfiguration of RocketIO™ transceiver attributes using the Virtex-II Pro™ internal configuration access port (ICAP). The solution uses a Virtex-II Pro device with an IBM PowerPC™ 405 (PPC405) processor to perform a partial reconfiguration of the RocketIO multi-gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes. These attributes must be modified to optimize the MGT signal transmission prior to and after a system has been deployed in the field. This solution is also ideal for characterization, calibration, and system testing. This product is not recommended for new designs.

Design File(s):

• xapp661.zip
• xapp661.zip

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design. This product is not recommended for new designs.

Design File(s):

• xapp529_6_1.zip
• xapp529_6_2.zip

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Package Drawing.

Design File(s):

• IPC-1752 Form

BG560 - Material Declaration Data Sheet (Standard Metal BGA)

Design File(s):

• IPC-1752 Form

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.