Virtex-II

All four modules of the data sheet plus a summary cover page compiled into a single PDF file.

All package files are ASCII files in zip format.

This document discusses timing models, design considerations, configuration, PCB design considerations, BitGen and PROMGen Switches and Options, and PROM information. This product is obsolete/under obsolescene.

Design File(s):

• xc2v_verilog.zip
• xc2v_vhdl.zip

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Virtex-II devices have shown possible issues with proper initialization of the device during power-up cycle.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

Xilinx is adding shipping trays produced by Kostat, Inc. for the new CS144/CSG144 and CS280/CSG280 Laminate packages.

A new thermal lid adhesive has been qualified for use on all flip-chip packages. The adhesion and thermal properties of the new material are comparable or better than the current thermal and lid attach adhesive.

A package substrate change for Chip Scale (Tape) and lead-free Chip Scale (Tape).

Design File(s):

• Qualification Report for XCN05018

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

This notification describes a change in the specification of the maximum configuration clock (CCLK) frequency in the SelectMAP mode from 66 MHz to 50 MHz for Virtex-II™ devices.

Updates include: corrected cross-ship date and indicated continued availability of ordering code SCD0765; removed references to 8-inch wafer ordering code SCD0769 (this SCD is now obsolete); clarified the bitstream programming file length paragraph; added traceability information; and modified Response and Contact Section.

The purpose of this advisory is to communicate that some Xilinx FPGAs in flip-chip packaging were manufactured using solder material that might cause random upset of device configuration bits.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain XC1700, XC4000E, XC4000XLA, XC5200, Spartan®-IIE, Spartan-3AN, Virtex®, Virtex-E, Virtex-II, CPLD and Aerospace & Defense “XQ” products.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

To communicate that the Xilinx discontinuation of certain Virtex® (Virtex-E, Virtex-EM, Virtex-II and EasyPath™ Virtex-II families) and Spartan® (Spartan-IIE family) FPGA products has been retracted due to a two year extension of production capability.

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

Design File(s):

• xapp753.zip

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

Design File(s):

• xapp693.zip
• xapp693.zip

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

Design File(s):

• xapp645.zip
• xapp645.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Design File(s):

• xapp482.zip
• xapp482.zip

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Design File(s):

• xapp229.zip
• xapp229.zip

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

Design File(s):

• xapp223.zip

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Design File(s):

• xapp211.zip
• xapp211.zip

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.

Design File(s):

• xapp1005.zip

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Design File(s):

• xapp500.zip

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

Design File(s):

• xapp694.zip

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

Design File(s):

• xapp291.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

Design File(s):

• xapp780.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note explains how to use the Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

Design File(s):

• xapp551.zip

This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transceiver of the Virtex-II Pro device or an external SERDES with either Virtex-II or Virtex-II Pro devices. This product is not recommended for new designs.

Design File(s):

• xapp687.zip
• xapp687.zip

This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink interface defines a set of protocol-agnostic signals that allows transmission of packet-oriented data, and enables a set of features such as flow control and transfer data of arbitrary length. The LocalLink FIFO consists of two LocalLink interfaces, one on the write port to interface with an upstream user application, the other on the read port to interface with a downstream user application. This product is not recommended for new designs.

Design File(s):

• xapp691.zip

The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the Gigabit Media Independent Interface (GMII). In this application note, an RGMII adaptation module is used to reduce the number of pins required to connect the Gigabit Ethernet MAC to a Gigabit PHY from 24 to 12. This product is not recommended for new designs.

Design File(s):

• xapp692.zip
• xapp692.zip

This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex™-II and Virtex-II Pro FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogiCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogiCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606). This product is not recommended for new designs.

Design File(s):

• xapp775.zip

This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs. This product is not recommended for new designs.

Design File(s):

• xapp774.zip

This application note shows how a Xilinx Virtex™-II or Virtex-II Pro device can connect to a Philips TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver. The reference design with this application note uses the TZA3015HW. This product is not recommended for new designs.

Design File(s):

• xapp764.zip

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design. This product is not recommended for new designs.

Design File(s):

• xapp933.zip

This application note and its accompanying reference design describe a dynamic phase alignment (DPA) module used in bus interfaces, such as SPI 4.2, using asynchronous data capture techniques. The DPA module can run at 800 Mbps and faster in Virtex™-II and Virtex-II Pro devices. It contains a word-alignment unit that can remove channel-to-channel skew. This document is an extension of XAPP671: High-Speed Data Recovery Using Asynchronous Data Capture Techniques. This product is not recommended for new designs.

Design File(s):

• xapp697.zip
• xapp697.zip

This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern-matching capabilities in the Virtex®-II, Virtex-II Pro, and Spartan®-3 architectures. This product is not recommended for new designs.

Design File(s):

• xapp690.zip
• xapp690.zip

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function. This product is not recommended for new designs.

Design File(s):

• xapp634.zip

This application note describes the implementation of R’G’B’ Color Space to Y’CbCr Color Space conversion necessary in many video designs. The tick marks on red, green, blue, and Luma, assume the components are in the gamma-corrected space. No gamma correction is applied to color difference signals Cr and Cb. This product is not recommended for new designs.

Design File(s):

• xapp637.zip

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design. This product is not recommended for new designs.

Design File(s):

• xapp529_6_1.zip
• xapp529_6_2.zip

Design File(s):

• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

100% Material Declaration Data Sheet BG575

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem, and offers some solutions.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

Describes how PCB design considerations play a major role in obtaining the expected performance from FPGAs. Focuses on early analysis and simulation methodologies as a way of performing a guided implementation. If design variables are analyzed and results passed to implementation, it is more likely the desired specifications will be met in the first pass, fulfilling the ultimate goal to keep development effort, cost, and time to a minimum.

This document provides an overview of the various usage models for high-speed, point-to-point, serial transceiver technology. While not intending to represent all the applications of this technology, it provides a basic categorization and description of some of the most common uses.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

Embedded systems see a steadily increasing bandwidth mismatch between raw processor MIPS and surrounding components. System performance is not solely dependent upon processor capability. While a processor with a higher MIPS specification can provide incremental system performance improvement, eventually the lagging surrounding components become a system performance bottleneck. This white paper examines some of the factors contributing to this. This document is obsolete/under obsolescence.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures. This product is obsolete/under obsolescence.

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

This document describes the features and operation of the Virtex™-II Prototype Platforms, including how to configure chains of FPGAs and serial PROMs. This product is obsolete/under obsolescence.

The MicroBlaze and Multimedia Development Board is designed to be used as a compact platform for developing multimedia applications. This document describes the features and operation of Virtex™-II MicroBlaze and Multimedia Development Board. This product is obsolete/under obsolescence.

Virtex-II LVDS Demonstration Board User Guide. This product is obsolete/under obsolescence.

Design File(s):

• ug019.zip