Virtex-II Pro

This application note describes a design that reduces latency through the receive elastic buffer of the Virtex™-II Pro RocketIO™ transceiver. This note is applicable only for designs that do not use the clock correction or channel-bonding features of the RocketIO transceiver. (These operations can still be done in the fabric, if needed.)

This application note describes a reference design to do a quantization and inverse quantization of MPEG-2 video signals. After a brief introduction, the process of using JPEG and MPEG-2 standards for quantizing matrices is developed. Finally, implementing the Xilinx solution for quantization or inverse quantization is described.

This application note describes a method for building a ROM firmware image residing in one location of memory and executing from/in another location. The examples given in this application note use the widely available GNU tools targeted for the PowerPC™ processor.

This application note discusses the usage of timing constraints in a Virtex®-II Pro design with the PowerPC™ 405 (PPC405) processor. The interaction of the timing constraints with the PPC405, Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), and RocketIO™ transceiver are described. The interactions are specified by the clock ratio between the busses and the designs processor block. The clock ratios between the PPC405 and PLB, and the PLB to the OPB are also discussed. A reference design is used to show the exact syntax of the timing constraints and Timing Analyzer results.

Data regeneration is an important function in RAID controllers and is best performed by dedicated hardware under the control of a microprocessor. The Virtex®-II Pro FPGA can perform both the hardware and software functions required for a RAID parity generator and data regeneration controller. This reference design uses burst mode SYNCBURST™SRAM memory accesses and an internal block SelectRAM™+ memory to provide an extremely efficient hardware design in a Virtex-II Pro FPGA.

This application note describes an alternative method for specifying Relatively Placed Macros (RPMs) using a new grid system called the "RPM Grid." This grid system can be used in the Virtex®-II architectures, including Virtex-II Pro devices. This is not a tutorial on how to create RPMs, and this document assumes some knowledge of how to create RPMs. (Please see the Xilinx Libraries Guide for details on capturing RPMs.) This application note describes how to use the RPM Grid to create a heterogeneous relocatable RPM macro containing both block RAM and slice components and demonstrates how this feature can be used to optimize the timing of paths from block RAM outputs to slice registers.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

This application note targets Virtex®-II Pro designs for which there is a requirement to directly use RocketIO™ transceivers in 16-bit mode. Use this reference design when 8b/10b data encoding is not required and the output frequency needs to be 16 times the system frequency.

Content Addressable Memory (CAM) offers increased data search speed. In various applications based on CAM, there are differing requirements for data organizations and read/write performance. The innovative design described in this application note is suited for small embedded CAMs with high-speed match and write requirements. The reference design is built using the true dual-port block SelectRAM™+ feature for the Virtex®-II series, including the Virtex-II Pro devices.

This application note describes three ways to implement the Y'CrCb Color Space to R'G'B' Color Space conversion necessary in many video designs.

The Virtex®-II FPGA series provides dedicated on-chip blocks of 18 Kbit True Dual-Port synchronous RAM for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 to 36 FIFO, with the depth and width being adjustable within the Verilog or VHDL code.

Huffman coding is used to code values statistically according to their probability of occurence. Short code words are assigned to highly probable values and long code words to less probable values. Huffman coding is used in MPEG-2 to further compress the bitstream. This application note describes how Huffman coding is done in MPEG-2 and its implementation.

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.

The shift registers available in Virtex®-II devices are ideal when building synchronous FIFOs. By using the flexibility of the shift register LUT primitive (SRL16), FIFOs can be built with any width while producing a 1-bit resolution. With cascaded SRL16 shift registers (SRLC16), a flexible depth in multiples of 16 is available.

Quad Data Rate (QDR™Synchronous Static RAM (SRAM) is one of the highest bandwidth solutions available for networking and telecommunications applications. This low-cost, high-performance solution is ideal for applications requiring memory buffering, traffic management, look-up tables, or link lists. This application note describes an implementation of a QDR SRAM controller for Virtex®-II devices using a source synchronous solution.

This application note describes the different local clocking resources available in the Virtex®-II architecture. Along with a reference design, the document details how to use the local clocking resources in source-synchronous applications.

This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink interface defines a set of protocol-agnostic signals that allows transmission of packet-oriented data, and enables a set of features such as flow control and transfer data of arbitrary length. The LocalLink FIFO consists of two LocalLink interfaces, one on the write port to interface with an upstream user application, the other on the read port to interface with a downstream user application.

The Queue Manager Reference Design (QMRD) illustrates per-flow queuing for network processing applications, along with class-based flow control. The QMRD segments variable length frames into fixed length Fabric Protocol Data Units (PDUs) when configured for ingress queuing, and reassembles fixed length Fabric PDUs into variable length frames when configured for egress queuing. It provides command and status interfaces that can be connected to a traffic scheduler, providing a complete traffic queuing and scheduling solution.

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

This application note describes a 3X-oversampling reference design that provides a 200 Mb/s to 1000 Mb/s serial interface using the Virtex™-II Pro RocketIO™ multi-gigabit transceiver (MGT). The reference design implements a 3X-oversampling circuit at the back end of the MGT and is targeted for the Fibre Channel rate of 1.0625 Gb/s.

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

The DEBUGHALT controller is a small, yet versatile piece of FPGA logic that simplifies the startup process of the PowerPC™ 405 (PPC405) processors in systems that cannot have any memory at the reset vector, or in systems that completely run out of cache. This application note is accompanied by a reference design that demonstrates debug halt mode implemented in the embedded PPC405 processor available on Virtex-II Pro™ FPGAs. The DEBUGHALT controller design enables external control of the PPC405 processor through the JTAG interfa

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

This application note describes a DDR2 SDRAM memory interface for Virtex™-II Pro FPGAs.

This application note describes how to generate statistical profiling information from the IBM PowerPC 405D, which is embedded in some Virtex-II Pro™ FPGAs. Specifically, the application note details how to convert trace output files generated from the Agilent Technologies Trace Port Analyzer into a gprof (GNU profiler) readable format. The gprof tool is capable of generating a histogram of a program's functions and a call-graph table of those functions.

This application note covers the steps necessary to run the open source firmware, Universal Bootloader (U-Boot), and to use it to boot Linux on the embedded IBM PowerPC™ 405 (PPC405) processor available on Virtex-II Pro™ ML300 Evaluation Platforms.

This application note describes the implementation of a traffic groomer that bridges the system space between a network line port (in this case, Gigabit Ethernet frame traffic) and the Mesh Fabric Reference Design (MFRD).

This application note describes an embedded Simple Mail Transfer Protocol (SMTP) client reference design that demonstrates the capacity of a network-enabled embedded system to report on its status via E-mail. It describes how to set up the Platform Studio design environment for the PowerPC™ 405, configure the 10/100 Ethernet MAC core, and create the Board Support Package (BSP) for VxWorks®.

Today's serial backplane implementations support line rates ranging from 622 Mbps to 3.125 Gbps and are now approaching speeds in excess of 10 Gbps. A significant recent development is the emergence of standards to define serial backplanes. Whether proprietary or standards-based, serial backplanes present a very demanding signaling environment with high signal density, multiple connectors, and substantial trace lengths. Proving and characterizing the performance of any high-speed serial solution is critical, and MultiBERT provides a means of accomplishing this with Xilinx™ Multi-Gigabit Transceivers (MGTs).

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

This application note describes a 200 MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro™ XC2VP20 FF1152 –6 device.

Describes a working Virtex™-II Pro PowerPC™ system that uses the Dhrystone benchmark and the reference design on which the system runs.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note describes the transformation of multiple synchronous serial data streams to parallel data through a multi-channel serial-to-parallel converter.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

The inclusion of embedded processor cores in Xilinx FPGAs opens new doors for high-throughput digital signal processing applications. System Generator for DSP is a high-level modeling environment for designing custom DSP data paths with performance and efficiency comparable to hand-crafted designs. Because System Generator for DSP is tightly integrated with the Simulink® and MATHLAB® tools from The Mathworks, Inc., FPGA designs are implemented by users in a familiar setting without being overly concerned with underlying hardware details.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

The Xilinx Flip-Chip BGA package is the latest package offering for Xilinx high-performance FPGA products. Unlike traditional packaging in which the die is attached to the substrate face-up and the connection is made by using wire, the solder-bumped die-in Flip-Chip BGA is flipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the laminate substrate.

This application note describes the probability of a metastable event occuring in a Xilinx Virtex™-II Pro FPGA. The test circuit measures the Mean Time Between Failure (MTBF) of these metastable events.

This application note defines timing parameters required for the timing analysis of source synchronous and system synchronous applications. The parameters discussed in this application note are listed in Module 3 of the Virtex™-II and Virtex-II Pro™ data sheets. This application note explains the DCM clock phase accuracy parameters, system-synchronous pin-to-pin setup/hold with DCM parameters (TPSDCM and TPHDCM), and all source-synchronous parameters. Memory interfaces and the XGMII interface analyses are provided as examples

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

The oversampling module described in this application note performs 3/4/5/6X oversampling. The oversampling ratio is selectable during operation to facilitate multi-rate applications. It is designed to accept 20 bits of oversampled data and to output 10 bits of extracted data to the user interface. This module can be used with the Virtex-II Pro™ RocketIO™ Multi-Gigabit Transceiver (MGT) to achieve line rates of 200 Mb/s to 1000 Mb/s.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

The design described in this application note utilizes the Virtex-II Pro™ RocketIO™ transceivers, the Xilinx Aurora Protocol Engine, and the 1-Gigabit Ethernet MAC core to provide a bridge between Aurora and Gigabit Ethernet. In addition, it can act as a starting point for systems wishing to use either Gigabit Ethernet or Aurora for general data transfer. Target applications include connecting Aurora devices to legacy Gigabit Ethernet networks, testing Aurora devices using Gigabit Ethernet traffic, and building larger systems requiring Aurora or Gigabit Ethernet interfa

This application note describes a method for bypassing the AC coupling in Virtex™-II Pro X devices. Doing so allows use of the 10 Gb/s RocketIO™ Multi-Gigabit Transceiver (MGT) in DC-coupled over-sampling applications.

This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex-II™ and Virtex-II Pro™ FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogicCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogicCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606).

This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs.

This application note describes how to use a Virtex™-II Pro device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 270 MHz with data transfers at 540 Mb/s per pin.

This application note shows how a designer can very simply implement a battery with the Virtex-II™ series FPGAs for high bitstream security. It shows a number of Xilinx recommended designs.

This application note shows how a Xilinx Virtex-II™ or Virtex-II Pro™ device can connect to a Philips TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver. The reference design with this application note uses the TZA3015HW.

This application note describes the local clocking resources available in the Virtex-II Pro™ architecture for the RXRECCLK of the 3.125 Gb/s RocketIO™ MGTs.

This application note describes the implementation of a RocketIO X™ bit-error rate tester (XBERT) reference design. The reference design generates and verifies non-encoded high speed serial data on one or multiple point-to-point links (2.5 Gb/s to 10 Gb/s) between RocketIO X multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II Pro X FPGA.

This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO™ multi-gigabit transceiver (MGT) blocks in the Virtex™-II Pro FPGA family.

The serial transfer of data between devices on a board or cards on a backplane using the LVDS differential standard is well established. Existing cards need to be able to interface to newer technologies. This application note discusses two possible ways to interconnect standard LVDS transceivers with the Current Mode Logic (CML) technology used in Xilinx RocketIO™ multi-gigabit transceivers (MGTs) through AC coupling and DC coupling.

The embedded PowerPC™ 405 processor blocks in Virtex-II Pro™ devices with –7 speed grades can achieve speeds to 400 MHz. Special considerations are necessary when using the left processor in dual-processor devices. This application note describes these considerations and provides a necessary macro when operating the left processor at speeds greater than 350 MHz.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This application note demonstrates the use of the Multi-Channel OPB Synchronous DRAM controller in a MicroBlaze™ processor system.

This application note describes how to build a system that can be used for determining the optimal phase shift for a DDR memory feedback clock. In this system, the DDR memory is controlled by a controller that attaches to either the OPB or PLB and is used in an embedded microprocessor application. This reference system also uses a DCM that is configured so that the phase of its output clock can be changed while the system is running and a GPIO core that controls that phase shift. The GPIO output is controlled by a software application that can be run on a PPC or MicroBlaze™ microprocessor

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

This application note describes how to implement a Software UART using a few I/O lines of the Xilinx UltraController GPIO interface.

The Xilinx Mesh Fabric Reference Design is a development vehicle for full mesh line cards based on Virtex™-II Pro devices. The design is a fully parameterized IP component that lets designers partition a mesh fabric design into any combination of Virtex-II Pro devices.

This application note and its accompanying reference design describe a dynamic phase alignment (DPA) module used in bus interfaces, such as SPI 4.2, using asynchronous data capture techniques. The DPA module can run at 800 Mbps and faster in Virtex-II™ and Virtex-II Pro™ devices. It contains a word-alignment unit that can remove channel-to-channel skew. This document is an extension of XAPP671: High-Speed Data Recovery Using Asynchronous Data Capture Techniques.

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

The Gigabit Ethernet Aggregation reference design (EARD) demonstrates the aggregation of up to eight Gigabit Ethernet ports to SPI-4.2 with optional frame-mapped Generic Framing Procedure (GFP-F).

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the Gigabit Media Independent Interface (GMII). In this application note, an RGMII adaptation module is used to reduce the number of pins required to connect the Gigabit Ethernet MAC to a Gigabit PHY from 24 to 12.

This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern-matching capabilities in the Virtex™-II, Virtex-II Pro™, and Spartan™-3 architectures.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Designing high-speed memory interfaces is a challenging task. Xilinx makes it simple to design such interfaces using the Virtex-II™ and Virtex-II Pro™ FPGAs. This application note discusses the challenges presented by this task, together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. All examples used in this application note assume a DDR-1 interface on an XC2VP20FF1152-6 Virtex-II Pro FPGA. The interface speed is 200 MH.

This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transceiver of the Virtex-II Pro™ device or an external SERDES with either Virtex-II or Virtex-II Pro devices.

This application note provides implementation guidelines for DDR interfaces using the Digital Clock Manager (DCM) and local inversion clocking techniques for Virtex-II™ Pro devices.

The UltraController™ embedded processor is a complete reference design of a "lightweight" PowerPC™ microcontroler. A 32-bit I/O design is a simple block for integration into larger designs. It only requires a reset and clock input. The UltraController solution utilizes the available PowerPC processor(s) in the Virtex-II Pro™ device and several block RAMs. The UltraController design is available for a variety of applications including logic and data control, device configuration, system monitoring, and simple data manipulation.

This application note describes using asynchronous data capture techniques as a method for high-speed data recovery in Virtex™-II and Virtex-II Pro™ devices. The reference designs accompanying this application note show how data is recovered in an interface running at 622 Mb/s DDR with 0.3UI of jitter.

TCP/IP is a communication protocol stack designed to provide a reliable data stream between two hosts. It is a popular means of communicating data over a network. Most people use the protocol every day to check email, browse the web, instant message, and download files. TCP/IP is also becoming more utilized in embedded systems. This application note explores the use of an open source TCP/IP stack on the Virtex-II™ Pro PowerPC™ processor. An example reference design is provided allowing remote interaction with the peripherals on the Insight/Memec designed Virtex-II Pro development board.

This application note describes in-circuit partial reconfiguration of RocketIO™ transceiver attributes using the Virtex-II Pro™ internal configuration access port (ICAP). The solution uses a Virtex-II Pro device with an IBM PowerPC™ 405 (PPC405) processor to perform a partial reconfiguration of the RocketIO multi-gigabit transceivers (MGTs) pre-emphasis and differential swing control attributes. These attributes must be modified to optimize the MGT signal transmission prior to and after a system has been deployed in the field. This solution is also ideal for characterization, calibration, and system testing.

This application note describes the implementation of a RocketIO™ transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex-II Pro™ FPGA. To build a system, an IBM CoreConnect™ infrastructure connects the PowerPC™405 processor (PPC405) to external memory and other peripherals using the processor local bus (PLB) and device control register (DCR) buses. The reference design uses a two-channel Xilinx bit-error rate tester (XBERT) module for generating and verifying high-speed serial data transmitted and received by the RocketIO transceivers

This application note describes a pre-engineered solution for Virtex-II Pro™ devices using the IBM PowerPC™ 405 core to perform a partial reconfiguration of the RocketIO™ Multi-gigabit Transceivers (MGTs) pre-emphasis and differential swing control attributes. This solution is ideal for applications where these attributes must be modified to optimize the MGT signal transmission for various system environments while leaving the rest of the FPGA design unchanged. The hardware and software elements of this solution can be easily integrated into any Virtex-II Pro design. The associated reference design files provide support for all members of the Virtex-II Pro family.

This application note describes how to interface 3.3V I/O in a Virtex™-II Pro system design. Topics include using the LVDCI_33 I/O standard to interface to LVCMOS or LVTTL external interfaces, Peripheral Component Interface (PCI) bus interface solutions, device configuration, and other board-level design techniques.

An unused RocketIO MGT can be used as a frequency synthesizer, generating a low-jitter clock for use either in the FPGA or in the rest of the system.

This application note describes a reference design for a mixed-version IP router (MIR) servicing up to four gigabit Ethernet ports. MIRs are useful where several gigabit Ethernet networks are operating with a mixture of IPv4 and IPv6 hosts and routers attached directly to the networks, and further nodes reached via the routers. A particular benefit of an approach based on the Virtex-II Pro™ family is that the router’s functions can evolve smoothly, maintaining router performance as the organization migrates from IPv4 to IPv6 internally, and also as the Internet migrates external

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

This application note describes the logic to perform basic word alignment and deframing specifically for SONET/SDH systems, where data is being processed at 16-bits or 64-bits per clock cycle.

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

This application note describes a high-speed, optimized implementation of a Virtex-II™ pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in VHDL and Verilog.

This application note describes a transmitter module and a receiver module compatible with Analog Devices TigerSHARC TS20x digital signal processors (DSPs). These two macros allow double data-rate (DDR) communication of 128-bit words over a four-bit LVDS link at speeds up to 1000 Mb/s per line (500 MB/s) when a Virtex-II™ Pro grade -7 device is transmitting, and up to 500 Mb/s per line when a Virtex-II Pro grade -7 device is receiving.

This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one clock and 16 data channels). The design can be implemented in both Virtex-II™ and Virtex-II Pro™ FPGAs. The accompanying reference design files include an example implementation targeting a Virtex-II XC2V3000FF1152 -5 speed grade device.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

This application note describes the implementation of Variable Length Coding (VLC) on Xilinx devices. Zig-zag coding and run length coding are done in an MPEG-2 encoder. The zig-zag coding arranges the DCT coefficients in the order of increasing frequency. These coefficients are then coded as a run-length pair where the run is the number of occurrences of a value and the length is the amplitude.

This application note describes a reference design used to bridge one 4-channel Xilinx® SPI-4.2 (PL4) Core to four 1-channel SPI-3 (PL3) Link Layer Cores. The design is implemented in a Virtex®-II device.

This application note utilizes the Virtex®-II Pro transceivers and the Xilinx® Aurora Protocol Engine to provide a multi-ported interface to a shared memory system in a backplane environment. Multiprocessor systems are often encountered in backplane systems, and distributed processing applications require access to a shared memory across a backplane bus. Utilization of a hardware test-and-set lock mechanism, along with a software protocol to test for a semaphore grant prior to accessing the shared memory, guarantees atomic access to the shared memory.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

The AccelDSP Synthesis Tool offers great benefits in automation, acceleration, and visualization when converting algorithms into a fixed-point model for implementation on an FPGAs.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

With the availability of the Virtex-II Pro devices containing more than one PowerPC processor and MicroBlaze and PicoBlaze soft processor cores, it is important to understand the basics of multiprocessor systems. This document provides a background for building true multiprocessor systems. It is by no means a comprehensive discussion on the topic of multiprocessing. For more information see Parallel Computer Architecture by Culler and Singh, with Gupta.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

This document provides a concise overview of the subset of the MATLAB language, including operators, as well as built-in and toolbox functions supported by AccelDSP™ Synthesis Tool for algorithmic synthesis targeting Xilinx FPGAs.

Virtex-II Pro FPGAs provide Digital Clock Management circuitry to handle all clock management requirements at the device, board, and system level resulting in simplified designs and reduced costs.

Describes how PCB design considerations play a major role in obtaining the expected performance from FPGAs. Focuses on early analysis and simulation methodologies as a way of performing a guided implementation. If design variables are analyzed and results passed to implementation, it is more likely the desired specifications will be met in the first pass, fulfilling the ultimate goal to keep development effort, cost, and time to a minimum.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

This document can help designers obtain more accurate I/O timing data without the need for board-level IBIS or SPICE simulations. Until recently, Xilinx specified outputs into a lumped capacitive load. However, since rise and fall times force board interconnect to be considered transmission lines, a lumped capacitive load is no longer relevant (see the TechXclusives document on this for more detail).

The M2C-Accelerator extends the Xilinx AccelDSP™ Model-Based Design solution by converting floating-point MATLAB to fixed-point C++ for accelerated MBD verification eliminating a potential bottleneck.

AccelDSP™ Synthesis Tool with IP-Explorer technology eliminates the trial-and-error from using IP blocks by allowing the tool automatically to select from various macro-architectures.

The Physical Synthesis and Optimization tools in the Xilinx ISE software have been created to reexamine the structure of your FPGA design during the packing and placement phases of implementation.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures.

Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem, and offers some solutions.

As programmable logic devices (PLDs) increase in density and complexity, the combination of a feature-rich fabric and sophisticated design tools enables users to realize their performance goals in less time. Shorter design cycle times enable users to lower overall design costs and meet time-to-market requirements. This white paper highlights how the Virtex-II Pro™ FPGA and ISE6 design tool combination provides a 40% performance advantage over the nearest competitor, the Altera Stratix™ PLD.

Companies across a wide range of industries are witnessing a transition from parallel to high-speed serial I/O solutions to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements. Serial solutions will ultimately be deployed in nearly every type of electronic products imaginable, from chip-to-chip interfacing, backplane connectivity and system boards, to box-to-box communications. This document focuses on the dynamics of this transition in the connectivity solutions market.

The Virtex-II Pro™ Platform FPGA provides an attractive single-chip solution to serial transceiver design problems that previously required multiple devices. This white paper describes several different dedicated external SERDES devices, and presents alternative design solutions using the Virtex-II Pro Platform FPGA with RocketIO™ transceivers.

Today's data rates, exceeding 622 Mbps and reaching the 1 to 3.125 Gbps range across 20 inches or more of backplane trace, have made it challenging to pass data reliably over parallel buses. As a result, designers are now forced to shift from the use of parallel buses to utilizing more advanced serial interconnects; however, even serial technologies have limitations, especially at data rates beyond the 1 Gbps level, where new problems arise. This white paper presents methods of addressing these issues with programmable logic solutions for next generation serial backplanes.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.