Virtex

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

This application note describes the logic to perform basic word alignment and deframing specifically for SONET/SDH systems, where data is being processed at 16-bits or 64-bits per clock cycle.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

This application note discusses version 2.1i of the Xilinx Design Manager (DM) and Flow Engine (FE). In 2.1i, significant enhancements for DM/FE have focused on improving ease of use. A number of new features are provided, including "self-contained revisions" and the "Smart" Flow Engine.

With the release of M2.1i, Floorplanner supports the Virtex™ family of FPGAs. This application note illustrates how the major Virtex-specific architectural features, such as BlockRAMs, global clock buffers, DLLs, and carry logic, are represented within the Floorplanner GUI and how designers can manipulate a design containing these elements.

This application note presents information on version 2.1i of the FPGA Editor and how it differs from the previous version of EPIC. (For general FPGA Editor usage, refer to the FPGA Editor Guide.) This application note also discusses how to return to EPIC type actions for zoom and pan actions.

The 2.1i software includes improvements in the Trace, Timing Analyzer, FloorPlanner, Constraints Editor, and other implementation tools to help make the designing procedure easier for Virtex™ devices. This paper is devoted to describing some of the simple steps necessary to constrain a Virtex design with the 2.1i implementation tools. The paper explains how to constrain with a CLKDLL in Virtex and examines the new look of the Timing Analyzer Reports.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

This application note describes the use of partial reconfiguration in Virtex™ series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex SelectMAP interface as well as configuration and readback operations. An in-depth review of Xilinx Application Note XAPP138 is highly recommended.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

This application note describes the implementation of Linear Feedback Shift Registers (LFSR) using the SRL macro available in the Virtex™ and Virtex™-II series of FPGAs. The optimal implementations of a 15-bit LFSR, a 52-bit LFSR, and a 118-bit LFSR are also discussed.

Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices.

Triple Module Redundancy (TMR) combined with Single-Event Upset (SEU) correction through partial reconfiguration is a powerful and effective SEU mitigation strategy. This method is only supported for the Virtex™ series of Xilinx FPGAs. (Xilinx Application Note XAPP216 describes the use of Readback and Partial Configuration for SEU detection and correction.) This application note outlines the recommended design methodology for constructing and implementing TMR logic within the Virtex architecture.

This application note describes the transformation of multiple synchronous serial data streams to parallel data through a multi-channel serial-to-parallel converter.

Power consumption in Xilinx FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turn-off are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered to achieve successful designs.

This application note is an overview of the Virtex™ architecture, emphasizing data bit location in the configuration bitstream. Knowing bit locations is the basis for accessing and altering on-chip data. FPGA applications can be built that change or examine the functionality of the operating circuit without stopping the circuit loaded in the device. This application note includes a glossary.

This application note demonstrates using a boundary-scan (JTAG) interface to configure and readback Virtex™ FPGA devices. Virtex devices have boundary-scan features that are compatible with the IEEE Standard 1149.1. This application note is a complement to the configuration section in the Virtex Data Sheet and application note XAPP138: "Virtex Configuration and Readback." Review both the Virtex Data Sheet and XAPP138 prior to reading this document.

This application note is offered as complementary text to the Configuration section of the Virtex™ Data Sheet. It is strongly recommended that you review the Virtex Data Sheet prior to reading this application note. This application note first provides a comparison of how Virtex configuration and readback is different from previous Xilinx FPGAs, followed by a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For other device families, see XAPP150.) For additional data, see the Xilinx IBIS files.

The Virtex™ FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system-level design.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.

The Virtex® FPGA series provides dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 x 8 FIFO, with the depth and width being adjustable within the Verilog or VHDL code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade.

Content Addressable Memory (CAM) or associative memory, is a storage device, which can be addressed by its own contents. Each bit of CAM storage includes comparison logic. A data value input to the CAM is simultaneously compared with all the stored data. The match result is the corresponding address. A CAM operates as a data parallel processor. CAMs can be used to design Asynchronous Transfer Mode (ATM) switches. Implementing CAM in ATM applications is specifically described in this application note. As a reference, the application note XAPP201, “An Overview of Multiple CAM Designs in Virtex® Devices,” presents diverse approaches to implement CAM in other designs.

Content Addressable Memories (CAM) allow a fast search for specific data in a memory. Each application has different CAM requirements. A CAM design implemented in Virtex® slices offers a flexible approach to CAM depth and width based upon LUTs configured as Shift Registers. This application note describes a fast CAM design finding a match in a single clock cycle. Application Note XAPP201, "An Overview of Multiple CAM Designs in Virtex devices," discusses the diverse solutions available when implementing CAM and introduces the specific solution described in this application note.

CAM (Content Addressable Memory) offers increased data search speed. In various applications based on CAM, there are differing requirements for data organization and read/write performance. The innovative design described in this application note is suited for small embedded CAMs with high-speed match and write requirements. The reference design is built using the true Dual-Port block SelectRAM™+ feature of Virtex® FPGAs. Application Note XAPP201, "An Overview of Multiple CAM Designs in Virtex Devices," discusses the diverse solutions available when implementing CAM while introducing the specific solution described in this application note.

Cyclic Redundancy Check (CRC) is an error-checking code widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex® device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.

This application note provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog.

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

The Virtex® FPGA series includes a highly configurable, high-performance SelectIO™ resource to provide support for a wide variety of I/O standards. The SelectIO resource is a robust set of features including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility and SelectIO features and the design considerations described in this document can improve and simplify system level design. Appendix A is a SelectIO update for both the Virtex-E and Virtex-E Extended Memory (Virtex-EM) product families. Appendix B is the Virtex-E and the Virtex-EM LVDS and LVPECL SelectIO design guide.

Digital-to-analog converters (DACs) convert a binary number into a voltage directly proportional to the value of the binary number. A variety of applications use DACs, including waveform generators and programmable voltage sources. This application note describes a Delta-Sigma DAC implemented in a Virtex® FPGA. The only external circuitry required is a low pass filter comprised of just one resistor and one capacitor. Internal resource requirements are also minimal.

When digital systems are used in real-world applications, it is often necessary to convert an analog voltage level to a binary number. The value of this number is directly or inversely proportional to the voltage. The analog to digital converter (ADC) described here uses a Virtex® FPGA, an analog comparator, and a few resistors and capacitors. An 8-bit ADC can be implemented in about 16 Virtex CLBs, and a 10-bit ADC requires about 19 CLBs.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

HSTL is a technology-independent interface standard for digital integrated circuits. It is a JEDEC standard developed for voltage scalable and technology independent I/O structures. The I/O structures required by this standard are differential amplifier inputs (with one input internally tied to a user-supplied input reference voltage, VREF for single-ended inputs) and outputs using output power supply inputs (VCCO) that may differ from those operating the device itself.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.