Virtex

All package files are ASCII files in zip format.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

Xilinx is adding shipping trays produced by Kostat, Inc. for the new CS144/CSG144 and CS280/CSG280 Laminate packages.

A package substrate change for Chip Scale (Tape) and lead-free Chip Scale (Tape).

Design File(s):

• Qualification Report for XCN05018

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

Clarification on Handling Unconnected VCCINT Pins for Virtex Devices

PCN2000-08: Additional equivalent wafer foundries for fabrication of the Virtex commercial (C-grade and I-grade) product family

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

Clarification of wafer foundry transition dates for the Virtex product family

This notice describes the latest additions for obsolescence and should be considered in conjunction with previous discontinuance notices produced by Xilinx.

The purpose of this notification is to communicate that Xilinx is discontinuing certain XC3000, XC4000XL, XC5206, Virtex®, Spartan®-3 products, and Aerospace & Defense "XQ" products.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain XC1700, XC4000E, XC4000XLA, XC5200, Spartan®-IIE, Spartan-3AN, Virtex®, Virtex-E, Virtex-II, CPLD and Aerospace & Defense “XQ” products.

To communicate that Xilinx is discontinuing the original Spartan® and Virtex® FPGA products.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

This application note discusses version 2.1i of the Xilinx Design Manager (DM) and Flow Engine (FE). In 2.1i, significant enhancements for DM/FE have focused on improving ease of use. A number of new features are provided, including "self-contained revisions" and the "Smart" Flow Engine.

With the release of M2.1i, Floorplanner supports the Virtex™ family of FPGAs. This application note illustrates how the major Virtex-specific architectural features, such as BlockRAMs, global clock buffers, DLLs, and carry logic, are represented within the Floorplanner GUI and how designers can manipulate a design containing these elements.

This application note presents information on version 2.1i of the FPGA Editor and how it differs from the previous version of EPIC. (For general FPGA Editor usage, refer to the FPGA Editor Guide.) This application note also discusses how to return to EPIC type actions for zoom and pan actions.

The 2.1i software includes improvements in the Trace, Timing Analyzer, FloorPlanner, Constraints Editor, and other implementation tools to help make the designing procedure easier for Virtex™ devices. This paper is devoted to describing some of the simple steps necessary to constrain a Virtex design with the 2.1i implementation tools. The paper explains how to constrain with a CLKDLL in Virtex and examines the new look of the Timing Analyzer Reports.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

Design File(s):

• xapp223.zip

This application note describes the use of partial reconfiguration in Virtex™ series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex SelectMAP interface as well as configuration and readback operations. An in-depth review of Xilinx Application Note XAPP138 is highly recommended.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Design File(s):

• xapp211.zip
• xapp211.zip

Power consumption in Xilinx FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turn-off are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered to achieve successful designs.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For other device families, see XAPP150.) For additional data, see the Xilinx IBIS files.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

Design File(s):

• xapp694.zip

This application note provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog.

Design File(s):

• xapp215.zip
• xapp215.tar.gz

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices.

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design. This product is not recommended for new designs.

Design File(s):

• xapp933.zip

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function. This product is not recommended for new designs.

Design File(s):

• xapp634.zip

This application note describes the implementation of R’G’B’ Color Space to Y’CbCr Color Space conversion necessary in many video designs. The tick marks on red, green, blue, and Luma, assume the components are in the gamma-corrected space. No gamma correction is applied to color difference signals Cr and Cb. This product is not recommended for new designs.

Design File(s):

• xapp637.zip

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design. This product is not recommended for new designs.

Design File(s):

• xapp529_6_1.zip
• xapp529_6_2.zip

Design File(s):

• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

BG560 - Material Declaration Data Sheet (Standard Metal BGA)

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures. This product is obsolete/under obsolescence.

The Xilinx Prototype board allows experimentation with Virtex™ devices prior to committing to using them for specific applications. It allows designers to try Virtex features such as block RAM, DLLs, and the SelectI/O resource, with an off-the-shelf resource. The Xilinx Prototype board also facilitates learning the entire design flow from schematic capture or HDL to programming and verification of designs.