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Virtex Data Sheets

DateName
04/02/2001 Virtex 2.5V FPGA Introduction and Ordering Information(PDF, ver 2.5, 55 KB )
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12/09/2002 Virtex 2.5V FPGA Detailed Functional Description(PDF, ver 2.8.1, 233 KB )
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07/19/2002 Virtex 2.5V FPGA Pinout Tables(PDF, ver 2.8, 169 KB )
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09/10/2002 Virtex 2.5V FPGA DC and Switching Characteristics(PDF, ver 3.2, 168 KB )
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12/09/2002 Virtex 2.5V FPGA Complete Data Sheet (all four Modules)(PDF, ver , 551 KB )
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05/04/2001 Virtex Package/Device Pinout Files (ASCII) (zip)(ZIP, ver , 157 KB )

All package files are ASCII files in zip format.

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Virtex User Guides

DateName
01/27/2012 Device Reliability Report, Fourth Quarter 2011(PDF, ver 8.1, 2.2 MB )

Summary of the reliability test data and results for Xilinx devices updated four times per year.

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Virtex Customer Notices

DateName
02/26/2003 XCU2001-01 - Sample Availability Update for PCN2000-08 (PDF, ver 1.2, 133 KB )
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11/14/2002 XCU2000-03 - Addition of PPT as a Substrate Supplier(PDF, ver 1.0, 22 KB )
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09/19/2000 XCU2000-02 - Design Process Marginality on Virtex 32x1 Distributed SelectRAM (PDF, ver 1.0, 21 KB )
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07/16/2007 XCN07012 - License Plate Number (LPN) Added to All Customer Labels(PDF, ver 1.0, 164 KB )

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

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05/17/2006 XCN06013 - Addition of Kostat Shipping Tray for CS144/CSG144 and CS280/CSG280 Laminate BGA Packages(PDF, ver 1.1, 76 KB )

Xilinx is adding shipping trays produced by Kostat, Inc. for the new CS144/CSG144 and CS280/CSG280 Laminate packages.

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12/21/2007 XCN05018 - Package Substrate Change for Chip Scale (Tape) and Lead-Free Chip Scale (Tape)(PDF, ver 1.0.1, 130 KB )

A package substrate change for Chip Scale (Tape) and lead-free Chip Scale (Tape).

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08/07/2006 XCN05011 - Mold Compound & Die-Attach Epoxy Material Conversion(PDF, ver 2.0, 60 KB )

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

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07/01/1999 PDN99004 - Discontinuance of Die and Wafer Sales for all Xilinx Product Families(PDF, ver 1.0, 24 KB )
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12/06/2004 PCN2004-28 - Humidity Indicator Card (HIC) Change(PDF, ver 1.0, 161 KB )

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

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08/09/2004 PCN2004-12 - Clarification on Handling Unconnected VCCINT Pins for Virtex Devices (PDF, ver 1.0, 44 KB )

Clarification on Handling Unconnected VCCINT Pins for Virtex Devices

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12/06/2004 PCN2003-11 - Conversion to Green Material Set (Mold Compound and Die Attach Material)(PDF, ver 1.1, 72 KB )
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06/11/2002 PCN2002-08 - Change in shipping trays for CB packages(PDF, ver 1.0, 39 KB )
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01/31/2001 PCN2001-05 - Functionality of the distributed (LUT-based) SelectRAM when configured in a 32x1 mode(PDF, ver 1.0, 19 KB )
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12/29/2000 PCN2000-08 Data - Qualification Data(PDF, ver 1.0, 11 KB )
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11/25/2003 PCN2000-08 - Additional equivalent wafer foundries for Virtex(PDF, ver 1.2, 33 KB )

PCN2000-08: Additional equivalent wafer foundries for fabrication of the Virtex commercial (C-grade and I-grade) product family

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08/03/2000 PCN00003 - A Change in the die-attach material for all thermally enhanced BGA packages(PDF, ver 1.0, 20 KB )
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08/19/2003 Advisory 2003-02 - Change in BGA Shipping Trays(PDF, ver 1.0, 43 KB )

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

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11/10/2003 Advisory 2003-01A - An update to Advisory 2003-01(PDF, ver 1.0, 69 KB )

Clarification of wafer foundry transition dates for the Virtex product family

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11/10/2003 Advisory 2003-01 - Clarification of wafer foundry transition dates for the Virtex product family(PDF, ver 1.1, 37 KB )
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04/26/2010 XCN07010 - Product Discontinuance Update(PDF, ver 1.1, 77 KB )

This notice describes the latest additions for obsolescence and should be considered in conjunction with previous discontinuance notices produced by Xilinx.

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04/27/2010 XCN08011 - Product Discontinuation Notice(PDF, ver 1.2, 155 KB )

The purpose of this notification is to communicate that Xilinx is discontinuing certain XC3000, XC4000XL, XC5206, Virtex®, Spartan®-3 products, and Aerospace & Defense "XQ" products.

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12/07/2009 XCN09033 - Humidity Indicator Card (HIC) Change(PDF, ver 1.0, 67 KB )

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

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07/19/2010 XCN09001 - Product Discontinuation Notice(PDF, ver 1.4.2, 259 KB )

To communicate that Xilinx is discontinuing certain XC1700, XC4000E, XC4000XLA, XC5200, Spartan®-IIE, Spartan-3AN, Virtex®, Virtex-E, Virtex-II, CPLD and Aerospace & Defense “XQ” products.

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10/18/2010 XCN10016 - Product Discontinuation Notice(PDF, ver 1.0, 283 KB )

To communicate that Xilinx is discontinuing the original Spartan® and Virtex® FPGA products.

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07/25/2011 XCN11018 - Spartan, Virtex and CoolRunner Series Wire Bond BGA Packaging Material Source Addition(PDF, ver 2.0, 147 KB )

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

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Virtex Application Notes

DateName
10/30/2007 XAPP689 - Managing Ground Bounce in Large FPGAs(PDF, ver 1.2, 90 KB )

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

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10/02/2007 XAPP501 - Configuration Quick Start Guidelines(PDF, ver 1.5, 249 KB )

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

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09/09/2006 XAPP441 - Remote FPGA Reconfiguration Using MicroBlaze or PowerPC(PDF, ver 1.1, 480 KB )

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

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09/27/1999 XAPP403 - Using the Version 2.1i Xilinx Design Manager and Flow Engine (DMFE)(PDF, ver 1.0, 169 KB )

This application note discusses version 2.1i of the Xilinx Design Manager (DM) and Flow Engine (FE). In 2.1i, significant enhancements for DM/FE have focused on improving ease of use. A number of new features are provided, including "self-contained revisions" and the "Smart" Flow Engine.

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10/13/1999 XAPP402 - 2.1i Floorplanner Support for Virtex FPGAs(PDF, ver 1.0, 514 KB )

With the release of M2.1i, Floorplanner supports the Virtex™ family of FPGAs. This application note illustrates how the major Virtex-specific architectural features, such as BlockRAMs, global clock buffers, DLLs, and carry logic, are represented within the Floorplanner GUI and how designers can manipulate a design containing these elements.

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10/13/1999 XAPP401 - 2.1i FPGA Editor(PDF, ver 1.0, 61 KB )

This application note presents information on version 2.1i of the FPGA Editor and how it differs from the previous version of EPIC. (For general FPGA Editor usage, refer to the FPGA Editor Guide.) This application note also discusses how to return to EPIC type actions for zoom and pan actions.

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10/01/1999 XAPP400 - Constraining Virtex Design in 2.1i(PDF, ver 1.0, 127 KB )

The 2.1i software includes improvements in the Trace, Timing Analyzer, FloorPlanner, Constraints Editor, and other implementation tools to help make the designing procedure easier for Virtex™ devices. This paper is devoted to describing some of the simple steps necessary to constrain a Virtex design with the 2.1i implementation tools. The paper explains how to constrain with a CLKDLL in Virtex and examines the new look of the Timing Analyzer Reports.

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12/03/2007 XAPP290 - Difference-Based Partial Reconfiguration(PDF, ver 2.0, 305 KB )

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

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02/18/2008 XAPP225 - Data to Clock Phase Alignment(PDF, ver 1.3, 153 KB )

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

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07/11/2005 XAPP224 - Data Recovery(PDF, ver 2.5, 206 KB )

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

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04/24/2008 XAPP223 - 200 MHz UART with Internal 16-Byte Buffer(PDF, ver 1.2, 169 KB )

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

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06/01/2000 XAPP216 - Correcting Single-Event Upsets Through Virtex Partial Configuration(PDF, ver 1.0, 109 KB )

This application note describes the use of partial reconfiguration in Virtex™ series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex SelectMAP interface as well as configuration and readback operations. An in-depth review of Xilinx Application Note XAPP138 is highly recommended.

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06/14/2004 XAPP211 - PN Generators Using the SRL Macro(PDF, ver 1.2, 111 KB )

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

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08/05/2002 XAPP158 - Powering Virtex FPGAs(PDF, ver 1.5, 95 KB )

Power consumption in Xilinx FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turn-off are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered to achieve successful designs.

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01/04/1999 XAPP135 - Virtex I/V Curves for Various Output Options(PDF, ver 1.0, 34 KB )

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For other device families, see XAPP150.) For additional data, see the Xilinx IBIS files.

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12/20/2007 XAPP104 - A Quick JTAG ISP Checklist(PDF, ver 3.0.1, 55 KB )

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

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03/06/2009 XAPP058 - Xilinx In-System Programming Using an Embedded Microcontroller(PDF, ver 4.1, 641 KB )

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

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11/19/2007 XAPP694 - Reading User Data from Configuration PROMs(PDF, ver 1.1.1, 244 KB )

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

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06/28/2000 XAPP215 - Design Tips for HDL Implementation of Arithmetic Functions(PDF, ver 1.0, 118 KB )

This application note provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog.

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09/24/2002 XAPP228 - Quad-Port Memories in Virtex Devices (PDF, ver 1.0, 61 KB )

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

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08/24/2009 XAPP502 - Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode(PDF, ver 1.6.1, 356 KB )

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

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07/28/2010 XAPP932 Chroma Resampler(PDF, ver 1.0.1, 514 KB )

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

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09/23/1999 XAPP201 - An Overview of Multiple CAM Designs in Virtex Devices(PDF, ver 1.1, 47 KB )

Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices.

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10/23/2007 XAPP933 - Two-Dimensional Linear Filtering - Not Recommended for New Designs(application/x-download, ver 1.1, 213 KB )

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design. This product is not recommended for new designs.

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10/26/2004 XAPP634 - Analog Devices TigerSHARC Link - Not Recommended for New Designs(application/x-download, ver 1.2, 60 KB )

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function. This product is not recommended for new designs.

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09/12/2002 XAPP637 - Color Space Converter: R’G’B’ to Y’CbCr - Not Recommended for New Designs(application/x-download, ver 1.0, 63 KB )

This application note describes the implementation of R’G’B’ Color Space to Y’CbCr Color Space conversion necessary in many video designs. The tick marks on red, green, blue, and Luma, assume the components are in the gamma-corrected space. No gamma correction is applied to color difference signals Cr and Cb. This product is not recommended for new designs.

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05/12/2004 XAPP529 - Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link(FSL) - Not Recommended for New Designs(application/x-download, ver 1.3, 162 KB )

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design. This product is not recommended for new designs.

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Virtex Package Specifications

DateName
01/08/2007 BGG432 - Material Declaration Data Sheet (Pb-free Metal BGA Cavity Down)(PDF, ver 1.0.1, 87 KB )

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01/08/2007 BG432 - Material Declaration Data Sheet (Standard Metal BGA Cavity Down)(PDF, ver 1.0.1, 81 KB )

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01/08/2007 BGG352 - Material Declaration Data Sheet (Pb-free Metal BGA Cavity Down)(PDF, ver 1.0.1, 83 KB )

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01/08/2007 BG352 - Material Declaration Data Sheet (Standard Metal BGA Cavity Down)(PDF, ver 1.0.1, 81 KB )

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10/03/2006 TQ144 - Material Declaration Data Sheet (Standard TQFP)(PDF, ver 1.2, 81 KB )

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10/19/2006 PQ240 - Material Declaration Data Sheet (Standard PQFP)(PDF, ver 1.2.1, 84 KB )

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10/03/2006 HQ240 - Material Declaration Data Sheet (Standard Heat Sink PQFP)(PDF, ver 1.2, 82 KB )

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06/18/2004 PQ240/PQG240 - Package Drawing (PQFP)(PDF, ver 1.2, 154 KB )
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02/20/2007 BGG560 - Material Declaration Data Sheet (Pb-Free Metal BGA)(PDF, ver 1.0, 86 KB )

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01/15/2007 BGG256 - Material Declaration Data Sheet (Pb-free Plastic BGA)(PDF, ver 1.0, 37 KB )

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09/25/2006 FG680 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)(PDF, ver 1.2, 88 KB )

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09/14/2006 FG256 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)(PDF, ver 1.2, 84 KB )

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09/28/2006 CS144 - Material Declaration Data Sheet (Standard Laminate Chip Scale BGA)(PDF, ver 1.2, 81 KB )

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01/08/2007 BG256 - Material Declaration Data Sheet (Standard Plastic BGA)(PDF, ver 1.2.1, 79 KB )

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10/19/2006 PQG240 - Material Declaration Data Sheet (Pb-free PQFP)(PDF, ver 1.2.1, 83 KB )

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09/28/2006 HQG240 - Material Declaration Data Sheet (Pb-free Heat Sink PQFP)(PDF, ver 1.2, 81 KB )

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09/22/2006 FGG680 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)(PDF, ver 1.2, 90 KB )

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09/27/2006 FGG676 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)(PDF, ver 1.2, 85 KB )

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06/29/2006 FGG256 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)(PDF, ver 1.1, 91 KB )

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09/28/2006 CSG144 - Material Declaration Data Sheet (Pb-free Laminate Chip Scale BGA)(PDF, ver 1.2, 85 KB )

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06/18/2004 HT144/HTG144 - Package Drawing (Heat Sink TQFP)(PDF, ver 1.2, 148 KB )
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06/18/2004 HQ240/HQG240 - Package Drawing (Heat Sink PQFP)(PDF, ver 1.2, 155 KB )
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04/12/2005 FG680/FGG680 - Package Drawing (Fine-Pitch BGA)(PDF, ver 1.2.1, 126 KB )
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03/23/2005 FG456/FGG456 - Package Drawing (Fine-Pitch BGA)(PDF, ver 1.2.1, 110 KB )
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04/12/2005 FG256/FGG256 - Package Drawing (Fine-Pitch BGA)(PDF, ver 1.2.1, 97 KB )
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05/31/2006 CS144/CSG144 - Package Drawing (Laminate Chip Scale BGA)(PDF, ver 1.1, 69 KB )
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01/15/2007 CS144/CSG144 - Package Drawing (Flex Tape Chip Scale BGA)(PDF, ver 1.3, 49 KB )
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04/06/2001 BG560 - Package Drawing (Standard Metal BGA)(PDF, ver 1.1, 54 KB )
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04/06/2001 BG432 - Package Drawing (Standard Metal BGA Cavity Down)(PDF, ver 1.1, 54 KB )
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04/06/2001 BG352 - Package Drawing (Standard Metal BGA Cavity Down)(PDF, ver 1.1, 50 KB )
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03/19/2007 BG256/BGG256 - Package Drawing (Plastic BGA)(PDF, ver 1.3, 98 KB )
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06/18/2004 TQ144/TQG144 - Package Drawing (TQFP)(PDF, ver 1.2, 147 KB )
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10/19/2006 TQG144 - Material Declaration Data Sheet (Pb-free TQFP)(PDF, ver 1.2.1, 80 KB )

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09/25/2006 FG676 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)(PDF, ver 1.2, 84 KB )

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06/15/2011 FG676/FGG676 - Package Drawing (Fine-Pitch BGA)(PDF, ver 1.3, 134 KB )
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10/05/2011 BG560 - Material Declaration Data Sheet (Standard Metal BGA)(PDF, ver 1.3, 136 KB )

BG560 - Material Declaration Data Sheet (Standard Metal BGA)

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01/19/2012 FGG456 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)(PDF, ver 1.4, 103 KB )

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01/19/2012 FG456 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)(PDF, ver 1.3, 101 KB )

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Virtex White Papers

DateName
02/27/2006 WP237 - What are OFFSET Constraints?(PDF, ver 1.0, 398 KB )

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

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05/12/2003 WP192 - SMT Package Rework(PDF, ver 1.0, 42 KB )

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

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10/22/2007 WP275 - Get your Priorities Right – Make your Design Up to 50% Smaller(PDF, ver 1.0.1, 239 KB )

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

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01/12/2004 WP209 - Virtex Variable-Input LUT Architecture - Obsolete(PDF, ver 1.0, 80 KB )

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures. This product is obsolete/under obsolescence.

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Virtex Board and Kit Documentation

DateName
12/09/1999 Virtex and Virtex-E Prototype Platforms User Guide(PDF, ver 1.1, 208 KB )

The Xilinx Prototype board allows experimentation with Virtex™ devices prior to committing to using them for specific applications. It allows designers to try Virtex features such as block RAM, DLLs, and the SelectI/O resource, with an off-the-shelf resource. The Xilinx Prototype board also facilitates learning the entire design flow from schematic capture or HDL to programming and verification of designs.

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