White Papers

Targeted design platforms are simpler, smarter, and more strategically viable design platforms that offer customers the optimum in flexibility, accessibility, applicability, and time to market.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

Considerable effort has been taken into reducing static power in the Virtex™-4 FPGAs. To this end, it is important to consider a realistic FPGA operating temperature.

This white paper provides a high-level overview of RTCA DO-254 and EUROCAE ED-80 and discusses how Xilinx can assist designers of avionics systems to achieve certification.

This White Paper examines ways to add custom hardware to a processor to achieve hardware acceleration without sacrificing performance of the processor or the bus to which it is attached.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

With the advent of platform FPGAs, programmable logic circuits provide an ever-growing set of architectural elements. Days when FPGAs were simply made of LUTs and flip-flops are long gone. Now FPGA fabric is "feature rich" and flexible. Sophisticated synthesis tools are required to further improve performance and logic utilization using these new architecture capabilities. This document presents some critical areas where Xilinx is actively working with synthesis partners to improve quality of results (QoR) while, at the same time, keeping design and verification processes as simple as possible.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This white paper explores solutions for implementing FIFOs in Virtex™-5 FPGAs.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

White Paper on the advantages and cost savings of using Xilinx CPLDs instead of 7400 Discrete Devices.

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This document describes how to use the CoolRunner XPLA3 timing model.

An overview of CoolRunner™-II CPLD applications in the Digital Video Applications market.

This document gives a detailed description of the CoolRunner XPLA3 clocking options.

This White Paper shows how the low power CoolRunner™-II CPLD can be used to incorporate new functionality into a portable educational toy quickly, cost effectively, and with very little additional power consumption.

This white paper describes methods for expanding the natural bit-width capability of dedicated multipliers in a way that will make best use of the complete FPGA resources.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This white paper provides examples to help your understanding of the capabilities and use of the SRL16E to improve the performance and lower the cost of your designs by as much as an order of magnitude.

This white paper discusses the use of CoolRunner™-II CPLDs in portable navigation devices.

This White Paper describes how Spartan®-3 FPGAs can reduce total system cost by up to 50% compared to competing FPGAs.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This paper explains the theory behind Reed-Solomon error correction, and discusses how a variety of practical Reed-Solomon encoding/decoding solutions can be implemented using Xilinx Spartan™-II family FPGAs.

This White Paper discusses applications for CoolRunner™-II CPLDs in POS and HPOS terminals.

This is a new and improved version of this article that first appeared two years ago. This updated flow includes new techniques, and updates to software flow and tools based on the latest ISE™ software and FPGA architectures.

With the proliferation of digital television more and more people around the world are beginning to distribute audio and video signals around their homes. For the home networking purists, Ethernet equipment offers inexpensive and proven products that can be bought at retail in both kit form or a la carte. Ethernet technology can reliably and efficiently network all the Internet appliances (PCs, printers, game consoles, digital televisions, security cameras, and much more) at home. Xilinx solutions enable these evolving technologies in consumer devices today.

This white paper discusses performance versus power consumption in 90 nm FPGAs and how the Virtex™-4 family provides the best of both worlds: high performance and low power consumption.

With the availability of the Virtex-II Pro devices containing more than one PowerPC processor and MicroBlaze and PicoBlaze soft processor cores, it is important to understand the basics of multiprocessor systems. This document provides a background for building true multiprocessor systems. It is by no means a comprehensive discussion on the topic of multiprocessing. For more information see Parallel Computer Architecture by Culler and Singh, with Gupta.

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

The innovative Virtex™-5 architecture, which is based on a real 6-input LUT with dual-LUT capability, provides substantial resource utilization advantages over competing architectures. This white paper details these advantages.

The variable-input look-up table (LUT) architecture has been a fundamental component of the Xilinx Virtex architecture first introduced in 1998. This unique architecture enables flexible implementation of any function with eight variable inputs, as well as implementation of more complex functions. In addition to being optimized for 4-, 5-, 6-, 7-, and 8-input LUT functions, the architecture is designed to support 32:1 multiplexers and Boolean functions with up to 79 inputs. The Virtex architecture enables users to implement these functions with minimal levels of logic. By collapsing levels of logic, users can achieve superior design performance. This performance leadership is validated by benchmarks that show Virtex with an average 38% performance leadership over alternative programmable logic architectures.

IBM and Xilinx recently announced a license agreement to develop programmable logic cores for use within the next generation IBM “Cu-08” ASIC product — this is a crucial link in the on-going quest for system-level integration. This collaboration to offer designers high-performance ASIC technology, with state-of-the-art programmable logic, opens a vast potential for new applications and the ultimate in both integration and flexibility. This development expands the growing relationship between these two leading technology companies. Both are ranked #1 in their product markets by Dataquest, where IBM has captured the #1 ASIC supplier ranking for 3 successive years, and Xilinx has similarly held the top FPGA supplier position.

This white paper describes the CoolRunner™ XPLA3 CPLD architecture.

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem, and offers some solutions.

As programmable logic devices (PLDs) increase in density and complexity, the combination of a feature-rich fabric and sophisticated design tools enables users to realize their performance goals in less time. Shorter design cycle times enable users to lower overall design costs and meet time-to-market requirements. This white paper highlights how the Virtex-II Pro™ FPGA and ISE6 design tool combination provides a 40% performance advantage over the nearest competitor, the Altera Stratix™ PLD.

Companies across a wide range of industries are witnessing a transition from parallel to high-speed serial I/O solutions to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements. Serial solutions will ultimately be deployed in nearly every type of electronic products imaginable, from chip-to-chip interfacing, backplane connectivity and system boards, to box-to-box communications. This document focuses on the dynamics of this transition in the connectivity solutions market.

This white paper gives an overall view of the various mainstream digital television standards and outlines related Forward Error Correction solutions available from Xilinx for cable, satellite, terrestrial, and mobile systems.

In today's world of modular networking and telecommunications design, it is becoming increasingly difficult to keep alignment with the many different and often changing interfaces, both inter-board and intra-board. Each manufacturer has their own spin on the way in which devices are connected. To satisfy the needs of our customers, we must be able to support all their interface requirements. For us to be able to make products for many customers, we must adopt a modular approach to the design. This modularity is the one issue that drives the major problem of shifting our bits from one modular interface to another.

A fundamental timing constraint is the PERIOD constraint. This paper discusses the overall purpose of PERIOD constraints and the specific paths that are covered by PERIOD constraints. Additionally, examples of timing reports are included with the common application of the PERIOD constraints.

As device sizes increase and operating frequencies rise, power consumption and thermal management become critical. The XPower tool from Xilinx allows users to perform the following tasks: Estimate a design’s power usage. Save settings in an XML file. Edit the XML file outside of XPower in a text editor. Open the XML file and its edited settings in XPower.

This paper first describes and positions various emerging in-vehicle standards and their respective strengths and weaknesses. It then explores the designer's dilemma: how to build flexible and scalable system architectures which will allow the time in market of telematics platforms match that of the host vehicle while still communicating internally and to other external systems. It then goes on to discuss enabling technologies and how to implement reconfigurable and upgradeable telematics platforms that can be designed for protocols today and in the future.

This document shows the level of performance that can be reached with Virtex™-5 family building blocks, with particular emphasis on the new ExpressFabric™ technology. The main features of this new technology, including the new 6-input LUT, are described.

This white paper compares and contrasts FPGA and microprocessor system design and development flows with the aim of helping the designer and definer of state-of-the-art electronics systems to make a considered and well informed architecture decision.

Spartan™-II FPGAs, programmed with IP cores, enable home networking products. Xilinx develops IP cores and partners with third-party IP providers to provide customers with a suite of cores to decrease the customer's time-to-market. While reprogrammability reduces the customer's time-to-market and enables flexibility, the Xilinx Online™ program allows time-in-market as specifications in emerging technologies keep evolving.

This white paper identifies the top design security threats, explores the basic levels of security, and describes how new, low-cost Spartan®-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

FPGAs have been used in DSP applications for years; more recently FPGAs have been emerging as ideal co-processors for standard DSP devices. FPGAs provide tremendous computational throughput by using highly parallel architectures, and are hardware reconfigurable, allowing the designer to develop customized architectures for ideal implementation of their algorithms. The new generation of FPGAs developed using 90-nm process technology provide the designer with an even more cost-effective solution. This white paper takes a look at some common high-performance DSP functions and calculates their effective implementation costs.

This document focuses on creating HDL code that maps efficiently onto the targeted device. The paper presents coding styles and tips to accelerate design performance. Proper FPGA coding practices are reiterated, and the lesser known techniques directly applicable to the latest Xilinx FPGA architectures are presented.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

A carefully designed Traffic Manager solution can be scaled and tailored to exactly match the needs of the customer in terms of logic; the customer only pays for the silicon needed. Hence, FPGAs provide the most cost-effective and high-performance solution in this market. Xilinx FPGAs provide the best solution.

Custom DSP algorithms are best modeled mathematically using MATLAB®, while complete systems are best modeled cycle-accurately using Simulink. The marriage of these two modeling domains provides an efficient means to design DSP systems into FPGAs.

The AccelDSP Synthesis Tool offers great benefits in automation, acceleration, and visualization when converting algorithms into a fixed-point model for implementation on an FPGAs.

This White Paper discusses the advantages of using DataGATE (input gating) over sleep modes.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

The M2C-Accelerator extends the Xilinx AccelDSP™ Model-Based Design solution by converting floating-point MATLAB to fixed-point C++ for accelerated MBD verification eliminating a potential bottleneck.

AccelDSP™ Synthesis Tool with IP-Explorer technology eliminates the trial-and-error from using IP blocks by allowing the tool automatically to select from various macro-architectures.

The Physical Synthesis and Optimization tools in the Xilinx ISE software have been created to reexamine the structure of your FPGA design during the packing and placement phases of implementation.

This white paper discusses the FPD market and looks in closer detail at Plasma Display Panels and Liquid Crystal Displays in particular. An overview of where Xilinx devices fit in digital video systems is followed by a market overview of the flat panel display industry. The value proposition for Xilinx devices is presented, followed by a detailed discussion of the relationship of product features and resources to FPD system requirements.

Virtex-II Pro FPGAs provide Digital Clock Management circuitry to handle all clock management requirements at the device, board, and system level resulting in simplified designs and reduced costs.

Describes how PCB design considerations play a major role in obtaining the expected performance from FPGAs. Focuses on early analysis and simulation methodologies as a way of performing a guided implementation. If design variables are analyzed and results passed to implementation, it is more likely the desired specifications will be met in the first pass, fulfilling the ultimate goal to keep development effort, cost, and time to a minimum.

Obsolescence is a concern of most design engineers and none more so than with automotive telematics equipment designers. Even though automotive electronics equipment design and development time scales have shrunk recently from 5 to 2 years, the products themselves will still need to be produced for many years and be active in the field or even longer.

Focuses on how Xilinx enables the automobile to be a more entertaining, more informative, and more productive environment. When we envisage automotive electronics we automatically consider electric windows, central locking systems, safety systems, climate control and electronic ignition systems, all of which require stringent qualification, temperature cycling, and certification. The new emerging automotive electronics boon has now shifted from under the hood or bonnet to in-cabin multimedia applications. The trend towards mobile offices and entertainment on the move has meant a large portion of the electronic or semiconductor content has moved into this expanding area.

The introduction of Spartan-3™ devices has created multiple changes in the evolution of embedded control designs and pushed processing capabilities to the “almost-free stage.” With these new FPGAs falling under $20, in volume, with over 1 million system gates, and under $5 for 100K gate-level units, any design with programmable logic has a readily available 8- or 16-bit processor costing less than 75 cents and 32-bit processor for less than $1.50. This white paper explores the benefits, system requirements, cost, design process, software and hardware architecture, and expansion strategy, along with many details of these systems.

Cell phone handsets (or “terminals,” as they’re called in Europe) are among the most dynamic products in the electronics market today. From their original analog roots, they have evolved into nearly pure digital devices with as much functionality as complex PDAs. Consumers who once evaluated handsets based on their ability to make high-quality local calls now take call clarity as a given. Their choices instead rest on characteristics ranging from a handset’s "skin" color to its ability to support streaming video. Buyers, even those shopping for low-cost handsets, increasingly demand these kinds of features: "extras" are well on their way to becoming standards. This shift puts manufacturers in a bind as they try to balance low cost with the ever-increasing consumer insistence on new features. Should customers pay for these features outright, or should their monthly payments subsidize the handset cost?

Shows how the Spartan-IIE family addresses the needs for lower cost and an increased number of I/Os. The Spartan-IIE family has been specifically designed for consumer designs with a heavy focus on total system cost, delivering the most I/O for the money. Additionally, the Spartan-IIE family offers a hassle free density migration path and a highly efficient I/O banking scheme, with substantial I/O standards to further reduce system cost.

This document demonstates the dramatic power savings that are obtained using the DataGATE feature.

This TechXclusive article gives an overview of voice data convergence technologies, the benefits to the users and some of the significant challenges facing the designers of these systems.

The Virtex-II Pro™ Platform FPGA provides an attractive single-chip solution to serial transceiver design problems that previously required multiple devices. This white paper describes several different dedicated external SERDES devices, and presents alternative design solutions using the Virtex-II Pro Platform FPGA with RocketIO™ transceivers.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

This document presents the different types of smart cards and their applications and discusses the variety of smart card readers available and what functions they can perform. An illustration of the elements that form a typical smart card reader and how and where CoolRunner devices can be used to undertake some of these tasks is described herein.

This paper focuses on how Xilinx Platform Flash PROMs simplify FPGA configuration design for system and board designers.

Spartan™-3 design performance is now slightly faster than Cyclone II when comparing the most cost effective speed grade in each device.

Describes Negative-Bias Temperature Instability (NTBI), an unwanted transistor behavior that is pervasive in all deep sub-micron designs.

This paper shows the level of performance that can be reached using Virtex™-4 FPGAs.

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.

This paper describes the synthesis and implementation tools strategies, such as Xplorer™, that can be employed to maximize design performance in actual designs with a detailed user constraints file (UCF) or benchmark designs where the user is evaluating the best achievable performance for a specified clock domain.

It doesn’t usually take very long to create an FPGA design. Recently, however, a Xilinx competitor ran an ad declaring that while an FPGA can take up to a year to design, it can be cloned in only a second. Are FPGA designs really that insecure? While the ad seems absurdly hyperbolic, it is true that the bitstreams of some volatile FPGAs can be cloned. While it’s unlikely that cloning could happen in "a second," fears about the insecurity of design efforts are valid ones. To alleviate these anxieties, this white paper will show you how to substantially secure the bitstream and the overall design of FPGAs using Xilinx CoolRunner™-II CPLDs.

The Xilinx Implementation Tools offer designers the flexibility and control over their design to enable quick time to market and increased clock speed. One feature of the software is Relationally Placed Macros (RPMs).

This white paper identifies the top design security threats, explores the advanced security options, and describes how new, low-cost Spartan™-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Today's data rates, exceeding 622 Mbps and reaching the 1 to 3.125 Gbps range across 20 inches or more of backplane trace, have made it challenging to pass data reliably over parallel buses. As a result, designers are now forced to shift from the use of parallel buses to utilizing more advanced serial interconnects; however, even serial technologies have limitations, especially at data rates beyond the 1 Gbps level, where new problems arise. This white paper presents methods of addressing these issues with programmable logic solutions for next generation serial backplanes.

This white paper offers design tips on changes that can be made to the FPGA environment, features, and tool options to optimize the system design power consumption, thus reducing thermal and power component cost as well as increasing overall system reliability.

This white paper discusses chip multiprocessing designs using the Xilinx Platform Studio

This white paper addresses power consumption in 65 nm FPGAs.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

Describes RPR as a network, explains how the MAC operates to provide required network functionality, gives a high-level view of the Virtex™-4 implementation of the MAC, including device sizing, and covers a few system design use cases.

This document can help designers obtain more accurate I/O timing data without the need for board-level IBIS or SPICE simulations. Until recently, Xilinx specified outputs into a lumped capacitive load. However, since rise and fall times force board interconnect to be considered transmission lines, a lumped capacitive load is no longer relevant (see the TechXclusives document on this for more detail).

New programmable logic circuits provide an evergrowing set of architectural elements. Advanced FPGAs are not solely made of look-up tables and flip-flops anymore, and today's logic fabrics are best described as “feature rich.” This trend requires sophisticated algorithms in both synthesis and implementation tools to provide optimal performance and logic utilization by leveraging these new hardware features. This document highlights how the Xilinx Virtex-II family provides 25% better logic utilization compared to Altera’s Stratix device family as a result of fabric features and advanced software algorithms.

The System ACE™ (Advanced Configuration Environment) CompactFlash configuration solution is designed to meet the growing need for flexible, high-density storage and configuration control.

HSTL is a technology-independent interface standard for digital integrated circuits. It is a JEDEC standard developed for voltage scalable and technology independent I/O structures. The I/O structures required by this standard are differential amplifier inputs (with one input internally tied to a user-supplied input reference voltage, VREF for single-ended inputs) and outputs using output power supply inputs (VCCO) that may differ from those operating the device itself.

This white paper describes Triple DES Encryption for certain Virtex-II devices. Review the white paper for more details.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

Using SystemGenerator, users can functionally simulate a design and use the MATLAB® environment to verify the bit/cycle-tru model against the golden reference results, produced either externally or inside the MATLAB environemnt.

A wireless home network is an intriguing alternative to phoneline and powerline wiring systems. Wireless home networks provide all the functionality of wireline networks without the physical constraints of the wire itself. They generally revolve around either IR or radio transmissions within your home. Radio transmissions comprise of two distinct technologies—narrowband and spread-spectrum radio. Most wireless home networking products are based upon the spread-spectrum technologies. To date, the high cost and impracticality of adding new wires have inhibited the wide spread adoption of home networking technologies. Wired technologies also do not allow users to roam about with portable devices. In addition, multiple, incompatible communication standards have limited acceptance of wireless networks in the home.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

Embedded systems see a steadily increasing bandwidth mismatch between raw processor MIPS and surrounding components. System performance is not solely dependent upon processor capability. While a processor with a higher MIPS specification can provide incremental system performance improvement, eventually the lagging surrounding components become a system performance bottleneck. This white paper examines some of the factors contributing to this.

This document provides an overview of the various usage models for high-speed, point-to-point, serial transceiver technology. While not intending to represent all the applications of this technology, it provides a basic categorization and description of some of the most common uses.

This document provides a concise overview of the subset of the MATLAB language, including operators, as well as built-in and toolbox functions supported by AccelDSP™ Synthesis Tool for algorithmic synthesis targeting Xilinx FPGAs.

The Xilinx Field Programmable Controller (FPC) solution allows you to create low-cost, customized processors with peripherals, memory, and logic — all on a single cost-optimized Spartan™-IIE FPGA. The FPC solution is ideal for applications in which cost and integration within a system is critical. With the flexibility to allow integration of other IP on the FPGA fabric, the Spartan-IIE family presents an ideal embedded solution. This white paper presents the end markets, FPC solution, and its associated tools, end applications, and the Spartan-IIE performance advantage.

When migrating or retargeting code from a previous design into a Virtex™-5 platform FPGA, some considerations should be addressed. This whitepaper identifies and details appropriate retargeting guidelines.

This White Paper describes CoolRunner™-II characteristics when powered by non-standard I/O voltages.

Today's connected society requires secure data encryption devices to preserve data privacy and authentication in critical applications. There is an immense value in integrating critical IP solutions like Discrete Cosine Transform/Inverse DCT (DCT/IDCT) and DES within a Xilinx Spartan-II FPGA to enhance performance and security in communication applications.

This white paper examines the industry's urgent need for higher rate interfaces (particularly 100 GbE), the important risks and concerns that a system architect has when adding 100 GbE to a platform, and several implementation options that show how FPGAs are uniquely positioned to handle these challenges.

This document provides a brief description of the Xilinx bitstream compression algorithm based on the LZ77 scheme. FPGA configuration files can be compressed by Xilinx-developed software to reduce memory storage requirements. Compressed configuration files can be stored in a high-density System ACE MPM FPGA configuration controller. The System ACE MPM controller decompresses the files and shifts the original configuration data to the target FPGAs.

This white paper covers the different kinds of IIR filters and structures, and, with the use of The MathWorks® tools, shows how these structures can be mapped to the Xilinx® FPGA architecture.

The FPGA Mezzanine Card (FMC) standard, developed by a consortium of companies ranging from FPGA vendors to end users, specifically targets FPGAs, increasing I/O flexibility and lowering costs in a broad range of applications.

This white paper describes how SmartXplorer and PlanAhead™ tools can help to achieve timing closure in the shortest amount of time by applying different design strategies and running them in parallel on different machines across a network.

FPGAs enabled with serial I/O offer the ideal balance of bandwidth, density, performance, flexibility, and cost for SoC designs. Xilinx offers a portfolio of serial I/O technology that addresses the full spectrum of bandwidth requirements for products ranging from commercial video displays to broadcast video ultra-high bandwidth wired telecommunications systems.

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, and Virtex-6 FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

This white paper discusses targeting guidelines and other considerations needed to achieve optimal designs with Spartan®-6 devices.

EasyPath®-6 FPGAs are the industry's only design-specific FPGA solution to offer seamless cost reduction for complex platform FPGA designs. Unlike traditional approaches that require design conversion to structured ASICs or standard-cell ASICs, the EasyPath-6 technology cost reduction is automatic, immediate, and entirely risk-free.