XC4000

Performance data (in terms of circuit speed) is provided for several key logic and routing functions implemented in XC4000XL-09 FPGAs, for purposes of overall system performance estimation. Performance data also is provided for equivalent implementations in the Altera FLEX 10K-2 family devices.

A simple method is presented for estimating power dissipation in XC4000X Series FPGAs. This method is targeted for early estimates during design conceptualization before detailed design information is available.

As an alternative to "gate counting", the capacity of look-up-table-based FPGAs can be measured more directly and objectively by examining the number of available "logic cells".

This paper examines some general concepts concerning Phase Locked Loop (PLL) usage and their application in programmable logic devices. A critique of a newly-announced PLL implementation for FPGAs also is included.

The new XC4000EX family includes large amounts of new routing resources, necessary to support today’s larger designs. These resources are detailed and compared with the XC4000E, and with ORCA devices from Lucent Technologies (formerly AT&T).

Xilinx XC4000E/EX offer a wide variety of memory configuration options from Address and Data width to Dual-Port operation.

The Xilinx XC4000 Select-RAM memory offers the best size flexibility and at the same time offers high speed operation with very little waste.

The Xilinx XC4000 Select-RAM memory offers the best size flexibility and at the same time offers high speed operation withvery little waste.

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block or blocks, you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block(s), you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

The use of the internal IOB 3-state control register can significantly improve output enable and disable time. This application note illustrates the use of hard macros to implement this register in both HDL and schematic-based designs.

This application note describes the basic flow and issues to note when performing HDL simulation with Alliance Series software. The goal of this document is to familiarize the user with some of the concepts, but it should not be considered a replacement for the Xilinx or HDL simulator documentation.

This paper describes design practices to synthesize high density designs (i.e., over 100,000 gates), composed of large functional blocks, for today's larger Xilinx FPGA devices using the Synopsys FPGA Compiler. The Synopsys FPGA Compiler version 1998.02, Alliance Series 1.5, and the XC4000X family were used in preparing the material for this application note.

This application note describes the mature Xilinx product families and highlights their differences.

In the Spartan™ XC3000, XC4000, and XC5200 device families, Xilinx offers several evolutionary and compatible generations of Field Programmable Gate Arrays (FPGAs). This overview describes two aspects of Xilinx FPGAs: What logic resources are available to the user, and how the devices are programmed.

Clarifies why the overshoot/undershoot limit includes both magnitude and duration. Applies to mature FPGA families only.

Beware of hold time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates.

All Xilinx SRAM-based FPGAs can be in-system configured and reconfigured an unlimited number of times. This application note describes the procedures for reconfiguring mature Xilinx FPGAs.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes XC4000XL/XLA and Spartan™-XL I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. However, such parameters are not production-tested and are, therefore, not guaranteed.

The XC4000E™/X and Spartan™ FPGA families provide distributed on-chip RAM. SelectRAM memory can be configured as level-sensitive or edge-triggered, single-port or dual-port RAM. The edge-triggered capability simplifies system timing and provides better performance for RAM-based designs. The dual-port mode offers new capabilities and simplifies FIFO designs.