XC5200

As an alternative to "gate counting", the capacity of look-up-table-based FPGAs can be measured more directly and objectively by examining the number of available "logic cells".

This application note describes the basic flow and issues to note when performing HDL simulation with Alliance Series software. The goal of this document is to familiarize the user with some of the concepts, but it should not be considered a replacement for the Xilinx or HDL simulator documentation.

This application note describes the mature Xilinx product families and highlights their differences.

In the Spartan™ XC3000, XC4000, and XC5200 device families, Xilinx offers several evolutionary and compatible generations of Field Programmable Gate Arrays (FPGAs). This overview describes two aspects of Xilinx FPGAs: What logic resources are available to the user, and how the devices are programmed.

Clarifies why the overshoot/undershoot limit includes both magnitude and duration. Applies to mature FPGA families only.

Beware of hold time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates.

All Xilinx SRAM-based FPGAs can be in-system configured and reconfigured an unlimited number of times. This application note describes the procedures for reconfiguring mature Xilinx FPGAs.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

This application note reviews the differences between the XC5200™ and XC2000™/XC3000™ families, recommends approaches for converting XC2000/XC3000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

This application note reviews the differences between the XC5200™ and XC4000™ families, recommends approaches for converting XC4000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

The phase comparator described in this application note permits phase-locked loops to be constructed using FPGA devices that require only an external voltage-controlled oscillator and integrating amplifier.

This application note discusses various approaches available for implementing state machines in FPGA devices, in particular, the one-hot-encoding scheme for medium-sized state machines.

XC4000/XC5200/Spartan FPGA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This application note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design.

This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small longline delay is eliminated, resulting in the fastest possible synchronous counter.