XC9500

This application note describes how to drive LEDs using Xilinx CPLDs.

Mixed signal systems require logic parts that can operate with two power supplies. XC9500™ CPLDs are designed to operate in either mixed 5V/3.3V systems or 5V-only systems. To handle both conditions, care has been taken to ensure that designers need not introduce elaborate circuitry to guarantee that 5V and 3.3V power supplies rise or fall in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these CPLDs.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes how to use the XC9500™ timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.