XC9500XL

This discussion focuses on comparing the Xilinx XC9500XL CPLD family with the Altera MAX7000A (including MAX7000AE) family. Both families address the high speed 3.3V ISP CPLD marketplace, where new developments in low voltage systems demand new solutions from CPLDs. The newer XC9500XL architecture may be viewed as a functional superset of the older Max7000A base architecture, and it provides more architectural flexibility, more logic resources, and a higher level of quality and reliability for new leading edge 3.3V systems.

This application note documents using a Xilinx® CPLD as a motor controller.

This application note describes how to drive LEDs using Xilinx CPLDs.

Checklist application note giving best practice CPLD design methodology.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This application note discusses the in-system programming speed of XC9500XL™ devices.

This application note describes how to properly configure XC9500XL CPLDs in 5V/3.3V mixed systems, 3.3V-only systems, and 3.3/2.5V mixed systems.

Previous generations of Xilinx FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex™ family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

Discovering electrical problems during the debug stage is too late. The printed circuit board has been built and may need significant changes to debug. The best approach is to avoid problems by planning for options at the outset. This application note provides a framework for checklisting a design early to eliminate problems.

This application note discusses XC9500XL™ CPLD power estimation and optimization and provides designers with an understanding of sense-amplifier-based CPLD power dissipation. The note also provides a brief discussion of the process for estimation. With this information, you can accurately assess the power dissipation for a design. Guidelines that permit you to make key choices to manage the power dissipation of your design and understand the package thermal limits are also presented.

This application note helps designers get the best results from XC9500XL™ CPLDs. Included are practical details on such topics as pin migration, timing, mixed voltage interfacing, power management, PCB layout, high speed considerations and JTAG best practices.

This application note describes the use of the XC9500XL™ timing model.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes the mature Xilinx product families and highlights their differences.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.