XAPP805 - Driving LEDs with Xilinx CPLDs (PDF)
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1.0 |
254 KB |
04/08/2005 |
XAPP501 - Configuration Quick Start Guidelines (PDF)
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This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families. Was this document helpful? Yes | No
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1.5 |
249 KB |
10/02/2007 |
XAPP440 - Power On Behavior of Xilinx CPLDs (PDF)
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1.0 |
85 KB |
05/25/2006 |
XAPP362 - Using the XC9500XV Timing Model (PDF)
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1.0 |
73 KB |
08/20/2001 |
XAPP361 - Planning for High Speed XC9500XV Designs (PDF)
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CPLD design has advanced significantly beyond that of fast PAL design. Today's CPLDs must operate in systems that include microprocessors, memories, I/O devices, buses, multiple power supplies and multiple frequency clocks. The actual logic design is frequently minor with respect to the electrical issues that must be dealt with during debug. Was this document helpful? Yes | No
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1.0 |
83 KB |
08/08/2001 |
XAPP143 - Using Verilog to Create CPLD Designs (PDF)
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This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided. Was this document helpful? Yes | No
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1.0 |
377 KB |
08/22/2001 |
XAPP137 - Configuring Virtex FPGAs from Parallel EPROMs with a CPLD (PDF)
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Previous generations of Xilinx FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex™ family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.
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1.0 |
81 KB |
03/01/1999 |
XAPP105 - A CPLD VHDL Introduction (PDF)
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This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs. Was this document helpful? Yes | No
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2.0 |
335 KB |
08/30/2001 |
XAPP104 - A Quick JTAG ISP Checklist (PDF)
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Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs. Was this document helpful? Yes | No
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3.0.1 |
55 KB |
12/20/2007 |
XAPP100 - Choosing a Xilinx Product Family (PDF)
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This application note describes the mature Xilinx product families and highlights their differences. Was this document helpful? Yes | No
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1.4 |
35 KB |
12/03/1998 |
XAPP070 - Using In-System Programming in Boundary-Scan Systems (PDF)
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This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices. Was this document helpful? Yes | No
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2.1.1 |
136 KB |
11/15/2007 |
XAPP069 - Using the XC9500 JTAG Boundary Scan Interface (PDF)
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This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming. Was this document helpful? Yes | No
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3.1 |
464 KB |
12/10/2002 |
XAPP067 - Using Serial Vector Format Files to Program XC9500 Devices In-System (PDF)
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This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files. Was this document helpful? Yes | No
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2.0 |
123 KB |
05/13/2002 |
XAPP058 - Xilinx In-System Programming Using an Embedded Microcontroller (PDF)
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The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.
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4.0 |
997 KB |
10/01/2007 |