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Changes in Vivado Design Suite 2013.3
Xilinx UG933 Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide Updated: Added new device information.
Xilinx EN257 XA Zynq-7000 All Programmable SoC: Production Errata, Errata Initial Xilinx release.
Xilinx DS190 Zynq-7000 All Programmable SoC Overview, Data Sheet Updated document; see revision history.
Xilinx XAPP1086 Developing Secure and Reliable Single FPGA Designs with Xilinx 7 Series FPGAs Using the Isolation Design Flow Updated: Minor revision.
Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices New Design Advisories
(Xilinx Answer 57930): "Design Advisory for Zynq-7000 SoC - Boundary Scan test fails when VMODE is set to 1.8V"
(Xilinx Answer 58694): "Design Advisory for Zynq-7000 SoC - Updated UG933 may require additional decoupling capacitors in some cases"