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Zynq-7000

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7 Series FPGAs Configurable Logic Block User Guide Updated with clarifications to the previous version.

AXI Chip2Chip Reference Design for Real-Time Video Applications Demonstrates real-time video traffic across two 7 series FPGA evaluation boards.

Zynq-7000 AP SoC, I2C - Standard Mode running faster than 90 kHz violates tHD; STA timing requirement New (or Updated) Design Advisory (or Advisories)
(Xilinx Answer 59366): "Zynq-7000 AP SoC, I2C - Standard Mode running faster than 90 kHz violates tHD; STA timing requirement"

Zynq-7000 AP SoC, SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories New (or Updated) Design Advisory (or Advisories)
(Xilinx Answer 61637): "Zynq-7000 AP SoC, SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories"

Zynq-7000 AP SoC, SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories New (or Updated) Design Advisory (or Advisories)
(Xilinx Answer 61638): "Zynq-7000 AP SoC, SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories"