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state of the art and easy-to-use tutorial modules. The objective
of the tutorial modules is to familiarize you with the new and
improved Xilinx design flows from design entry to verification
and debugging. A complete flow entails walking through:
- The EDA interface of choice module (Exemplar, Mentor,
Synopsys, Synplicity)
- Running the Implementation module (Place & Route)
- Running the H/W Debugger module
Foundation
The Watch Design Foundation Tutorial is a complete tutorial
using the Foundation F2.1i tools. The tutorial includes three
design entry formats (Schematic, VHDL and Verilog) and covers
Design Entry, Synthesis, Implementation and Simulation.
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Exemplar
The Watch Design Exemplar Tutorial is a flow based tutorial
taking the Verilog/VHDL Design files through Exemplar Leonardo
Spectrum 1998.2e for synthesis. The tutorial includes presynthesis
Functional Simulation, and a post place and route (PAR) Timing
Simulation, both using the Model Technology ModelSim simulator.
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Mentor
This is a schematic only tutorial designed to be used with Mentor
C.2 and Xilinx 2.1i. This tutorial will take you through setting
up the tutorial , the design flow, completing the Calc design,
and using the Xilinx Design Manager. It will also lead you through
a pre-2.1i functional simulation as well as a post-PAR Timing
simulation. This tutorial is based on the older Calc tutorial.
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Synopsys
These tutorials are for use on UNIX workstations. They are designed
to introduce the Alliance 2.1i XSI design flow. For synthesis,
FPGA Compiler must be used. For simulation, either VerilogXL
or VSS must be used. These tutorials go through the implementation
flow via command-line. For more detailed information on the
implementation flow, refer to the implementation tutorial.
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Synplicity
The Watch Design Synplicity Tutorial is a flow based tutorial
taking the Verilog/VHDL Design files through Synplicity Synplify
for synthesis. The tutorial includes presynthesis Functional
Simulation, and a post place and route (PAR) Timing Simulation,
both using the Model Technology ModelSim simulator.
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Implementation
This document demonstrates the steps in the 2.1i Alliance Series
design implementation (GUI) flow for the Watch design. Before
beginning this tutorial, you should have entered the Watch design
into the design entry tool of your choice.
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Hardware Debugger
This is the Hardware Debugger Tutorial for the Watch Design.
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