Designing a LogiCORE PCI Express System
Course Information
Course Description
By learning PCI Express core protocol fundamentals, designers will gain a working knowledge of how PCI Express can be used in their systems. This course focuses on the PCI Express protocol subjects that designers, using the Xilinx PCI Express core, should understand to complete their designs faster and more easily. Students will also be introduced to each Xilinx PCI Express core product and will gain intimate knowledge of how the PCI Express core operates.
Level
Intermediate
Training Duration
2 days
Who Should Attend?
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Hardware designers who want to create applications using Xilinx IP cores for PCI Express
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Software engineers who want to understand the deeper workings of the Xilinx LogiCORE PCI Express solution
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System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications
Prerequisites
- Comprehensive understanding of the PCIe protocol (2 hour review included)
- Solid knowledge of Verilog or VHDL
- Solid experience with commonly used simulation tools such as Mentor Graphics ModelSim or ISIM
- Basic knowledge of Xilinx ISE™ software
- Designing for Performance and Designing with Multi-Gigabit Serial I/O are recommended
Software Tools
- Xilinx ISE 9.2i
- ISIM 9.2i
- ChipScopePro9.2i
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Effectively use the Xilinx PCI Express cores in your own design environments
- Select the appropriate PCI solution for a specific application
- Identify how PCI Express specification requirements apply to using Xilinx PCI Express cores
Course Outline
Day 1
- Course Introduction
- Review of the PCIe System Architecture and Protocol
- PCIe and CORE Generator
- Lab 1: Constructing the PCIe Core
- Simulating a PCIe Design
- Connecting Logic to the Core – Local Link
- Lab 2a: Downstream Port Model Simulation
- Designing the Endpoint Application
- Lab 2b: Pseudo-Transactional Modeling
Day 2
- Lab 3: Implementing the Design
- Compliance and Debugging
- Lab 4: Debugging the PCIe Core with the ChipScope Pro Tools
- Errors and Interrupts
- Host Side –Applications and Drivers
- Lab 5: Running the System
- Mechanicals, Hot Plug, and Power
- Course Summary
Lab Descriptions
- Lab 1: Constructing the PCIe Core: Familiarizes you with all the necessary flow of the Xilinx CORE Generator™ software for generating a Xilinx LogiCORE™ Endpoint Block Plus IP. You will select appropriate parameters for the CORE Generator tool and create the PCIe core used throughout the labs
- Labs 2 a and b - Simulating the PCIe Core: Provides an overview of simulating the core using the ISIM tool. You will observe and capture the effects of link training and write packets to the endpoint application during the Downstream Port Model simulation. This data will be played back during a transactional module simulation lab.
- Lab 3: Implementing the Design: Familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.
- Lab 4: Debugging Strategies: Using a traffic simulator, you will use the ChipScope™ Pro tools to monitor the behavior of the core and the endpoint application for proper operation.
- Lab 5: Running the Application: You will modify C code to target the Configuration Space of the design that was implemented in the previous lab and execute an example program to exercise the endpoint.
To Register
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers:
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