Recorded Lectures: FPGA Design for ASIC Users
The FPGA Design for ASIC Users course will help you to create fast and efficient FPGA designs by leveraging your ASIC design experience. This course will help you avoid the most common design mistakes of FPGA designers. It will also help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, reduce your debug time, and lower development costs.
Level
FPGA 1
Training Duration
5 modules ~ 3 ½ hours
Who should attend?
ASIC or FPGA designers with limited or no FPGA design experience. Xilinx ISE® tool experience is not required.
Prerequisites
- Beginning HDL knowledge (VHDL or Verilog)
- Solid digital design background
- Basic HDL Coding Techniques recorded e-learning (part 1 and part 2)
- Some synthesis tool experience is recommended (Synplify or XST)
Note that HDL experience is recommended but no Xilinx ISE software tool experience is required.
Related Instructor-led Courses
Skills Gained
After completing this comprehensive ASIC FPGA training, you will have the necessary skills to:
- Identify the differences between ASIC and FPGA architectures
- Describe the architectural features of FPGAs
- Recognize the benefits of the dedicated hardware resources in FPGAs
- Explain the differences between ASIC and FPGA design flows, including verification and debugging
- Optimize your ASIC HDL code for implementation in an FPGA
- Avoid the most common design mistakes of FPGA designers
- Choose among the various FPGA design tools and identify their purpose
- Increase system performance and reduce your design size by using optimum HDL coding techniques for Virex®-5 and Spartan®-3 FPGAs (note that both are available, but designers usually choose one device family)
- Recognize the most common FPGA synthesis options and their appropriate use
Course Outline
- ASIC FPGA Technology Comparison
- ASIC FPGA Design Flow
- ASIC FPGA Coding Conversion
- Recommended: Spartan-3 FPGA Coding Techniques (part 1 and part 2) or Virtex-5 FPGA Coding Techniques (part 1 and part 2)
Describes the differences between ASIC and FPGA architectures and describes how these differences affect coding style, implementation, and product selection:
- Gate conversion
- Delays
- Frequency comparison
Also discusses reconfigurability.
Describes key differences between the FPGA and ASIC design flows
- Design methodology
- Verification techniques
- Test generation
- Logic Tools
Explains how to optimize ASIC code for implementation in Xilinx FPGAs:
- Xilinx special resources
- Xilinx combinatorial resources
- Xilinx synchronous resources
- Intellectual Property (IP)
Also describes the steps to perform ASIC to FPGA code conversion.
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