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Class Schedule By State

Course Information

Class Schedule by Location

Class Schedule by Course

Schedule updated November 10, 2009

Dates are subject to change. Contact your local training representative with any questions.

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Download the Class Schedule by Course (PDF)

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PlanAhead™ software
LogiCORE™ IP
Virtex® family
Spartan® family
AccelDSP™ synthesis tool

Internet Based Training
No classes scheduled for the next 4 months in this location. Request an Online Training Class

Alabama
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with VHDL	11/25/09-11/27/09	Contact ATP	1,800	18	Register
For this location, please visit our ATP's website: Hardent

Alberta
For this location, please visit our ATP's website: Hardent

Arizona
For this location, please visit our ATP's website: Technically Speaking

Arkansas
For this location, please visit our ATP's website: Faster Technology

British Columbia, Canada
For this location, please visit our ATP's website: Technically Speaking

California (Northern)
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with Multi-Gigabit Serial I/O	11/17/09-11/19/09	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
DSP Design Using System Generator	12/1/09-12/2/09	Xilinx Learning Center - San Jose, CA, USA	1,200	12	Register
Essentials of FPGA Design	12/1/09-12/1/09	Xilinx Learning Center - San Jose, CA, USA	500	5	Register
Designing for Performance	12/2/09-12/3/09	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
Designing with VHDL	12/8/09-12/10/09	Xilinx Learning Center - San Jose, CA, USA	1,500	15	Register
Advanced FPGA Implementation	12/15/09-12/16/09	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
Designing with the PlanAhead Analysis and Design Tool	12/15/09-12/16/09	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
Essentials of FPGA Design	2/9/10-2/9/10	Xilinx Learning Center - San Jose, CA, USA	500	5	Register
Designing for Performance	2/10/10-2/11/10	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
Essentials of FPGA Design	3/2/10-3/2/10	Xilinx Learning Center - San Jose, CA, USA	500	5	Register
Designing for Performance	3/3/10-3/4/10	Xilinx Learning Center - San Jose, CA, USA	1,000	10	Register
Can't find the class you are looking for?. Request a Private or Public Class

California (Southern)
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Essentials of FPGA Design	12/14/09-12/14/09	Holiday Inn - Costa Mesa Orange Co. Airport	600	6	Register
Designing for Performance	12/15/09-12/16/09	Holiday Inn - Costa Mesa Orange Co. Airport	1,200	12	Register
Designing with the Spartan-6 and Virtex-6 Families	1/26/10-1/28/10	Holiday Inn - Costa Mesa Orange Co. Airport	1,800	18	Register
For this location, please visit our ATP's website: Technically Speaking

Colorado
Request a Private or Public Class

Connecticut
For this location, please visit our ATP's website: Hardent

District Of Columbia
For this location, please visit our ATP's website: Bottom Line Technologies

Florida
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Embedded Systems Development	11/23/09-11/24/09	Contact Hardent	1,400	14	Register
Designing with the Spartan-6 and Virtex-6 Families	1/25/10-1/27/10	Contact Hardent	1,800	18	Register
Advanced FPGA Implementation	1/28/10-1/29/10	Contact Hardent	1,400	14	Register
For this location, please visit our ATP's website: Hardent

Georgia
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with VHDL	12/8/09-12/10/09	Hyatt Place Atlanta/Duluth/Johns Creek	1,800	18	Register
Designing with the PlanAhead Analysis and Design Tool	01/06/10-01/07/10	Hyatt Place Atlanta/Duluth/Johns Creek	1,400	14	Register
Embedded Systems Development	2/16/10-2/17/10	Hyatt Place Atlanta/Duluth/Johns Creek	1,400	14	Register
Designing with the Spartan-6 and Virtex-6 Families	2/23/10-2/25/10	Hyatt Place Atlanta/Duluth/Johns Creek	1,800	18	Register
For this location, please visit our ATP's website: Hardent

Idaho
For this location, please visit our ATP's website: Technically Speaking

Illinois
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Essentials of FPGA Design	2/22/10-2/22/10	Contact North Pole Engineering	600	6	Register
Designing for Performance	2/23/10-2/24/10	Contact North Pole Engineering	1,200	12	Register
DSP Design Using System Generator	2/25/10-2/26/10	Contact North Pole Engineering	1,200	12	Register
Designing with VHDL	3/1/10-3/3/10	Contact North Pole Engineering	1,800	18	Register
Advanced VHDL	3/4/10-3/5/10	Contact North Pole Engineering	1,200	12	Register
Designing with Verilog	3/8/10-3/10/10	Contact North Pole Engineering	1,800	18	Register
For this location, please visit our ATP's website: North Pole Engineering

Indiana
For this location, please visit our ATP's website: Vai Logic

Iowa
For this location, please visit our ATP's website: North Pole Engineering

Kansas
For this location, please visit our ATP's website: North Pole Engineering

Kentucky
For this location, please visit our ATP's website: Vai Logic

Louisiana
For this location, please visit our ATP's website: Faster Technology

Massachusetts
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with the Virtex-6 Family	11/17/09-11/19/09	Genesis Associates - Burlington, MA	1,800	18	Register
Fundamentals of FPGA Design	12/15/09-12/15/09	Genesis Associates - Burlington, MA	600	6	Register
Designing for Performance	12/16/09-12/17/09	Genesis Associates - Burlington, MA	1,300	13	Register
DSP Design Using System Generator	01/13/10-01/14/10	Genesis Associates - Burlington, MA	1,400	14	Register
Designing with the PlanAhead Analysis and Design Tool	2/10/10-2/11/10	Genesis Associates - Burlington, MA	1,400	14	Register
Designing with Ethernet MAC Controllers	3/9/10-3/10/10	Genesis Associates - Burlington, MA	1,600	16	Register
For this location, please visit our ATP's website: Hardent

Manitoba, Canada
For this location, please visit our ATP's website: Hardent

Maryland
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with the Spartan-6 and Virtex-6 Families	11/12/09-11/13/09	Genesis Mid-Atlantic - Columbia, MD - USA (14)	1,400	14	Register
Designing with Multi-Gigabit Serial I/O	12/10/09-12/11/09	Genesis Mid-Atlantic - Columbia, MD - USA (14)	1,400	14	Register
For this location, please visit our ATP's website: Bottom Line Technologies

Maine
For this location, please visit our ATP's website: Hardent

Michigan
For this location, please visit our ATP's website: Vai Logic

Minnesota
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
DSP Design Using System Generator	1/14/10-1/15/10	Contact North Pole Engineering	1,200	12	Register
Embedded Systems Software Development	1/18/10-1/19/10	Contact North Pole Engineering	1,200	12	Register
Designing with Verilog	1/20/10-1/22/10	Contact North Pole Engineering	1,800	18	Register
Embedded Systems Development	1/25/10-1/26/10	Contact North Pole Engineering	1,200	12	Register
Essentials of FPGA Design	1/27/10-1/27/10	Contact North Pole Engineering	600	6	Register
Designing for Performance	1/28/10-1/29/10	Contact North Pole Engineering	1,200	12	Register
Designing with VHDL	2/1/10-2/3/10	Contact North Pole Engineering	1,800	18	Register
Advanced VHDL	2/8/10-2/9/10	Contact North Pole Engineering	1,000	10	Register
Designing with the Spartan-6 and Virtex-6 Families	2/10/10-2/12/10	Contact North Pole Engineering	1,800	18	Register
For this location, please visit our ATP's website: North Pole Engineering

Missouri
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Embedded Systems Software Development	11/16/09-11/17/09	Contact North Pole Engineering	1,200	12	Register
Designing with Verilog	11/18/09-11/20/09	Contact North Pole Engineering	1,800	18	Register
Designing with VHDL	11/30/09-12/2/09	Contact North Pole Engineering	1,800	18	Register
Advanced VHDL	12/3/09-12/4/09	Contact North Pole Engineering	1,200	12	Register
Designing with the Spartan-6 and Virtex-6 Families	12/8/09-12/10/09	Contact North Pole Engineering	1,800	18	Register
For this location, please visit our ATP's website: North Pole Engineering

Mississippi
For this location, please visit our ATP's website: Hardent

Nebraska
For this location, please visit our ATP's website: North Pole Engineering

Nevada
For this location, please visit our ATP's website: Technically Speaking

New Hampshire
For this location, please visit our ATP's website: Hardent

New Jersey
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with the PlanAhead Analysis and Design Tool	11/12/09-11/13/09	Contact Bottom Line Technologies	1,400	14	Register
Embedded Systems Development	12/1/09-12/2/09	Contact Bottom Line Technologies	1,400	14	Register
Advanced Features and Techniques of Embedded Systems Development	12/3/09-12/4/09	Contact Bottom Line Technologies	1,400	14	Register
Embedded Systems Software Development	12/8/09-12/9/09	Contact Bottom Line Technologies	1,400	14	Register
Embedded Open-Source Linux Development	12/10/09-12/11/09	Contact Bottom Line Technologies	1,400	14	Register
For this location, please visit our ATP's website: Bottom Line Technologies

New Mexico
For this location, please visit our ATP's website: Technically Speaking

New York
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing for Performance	11/19/09-11/20/09	Avnet - Rochester, NY	1,400	14	Register
For this location, please visit our ATP's website: Bottom Line Technologies

North Carolina
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
DSP Implementation Techniques for Xilinx FPGAs	1/13/10-1/15/10	Contact Hardent	2,100	21	Register
Designing with VHDL	3/1/10-3/3/10	Contact Hardent	1,800	18	Register
Designing with the PlanAhead Analysis and Design Tool	3/4/10-3/5/10	Contact Hardent	1,400	14	Register
For this location, please visit our ATP's website: Hardent

North Dakota
For this location, please visit our ATP's website: North Pole Engineering

Ohio
For this location, please visit our ATP's website: Vai Logic

Oklahoma
For this location, please visit our ATP's website: Faster Technology

Ontario, Canada
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Advanced VHDL	11/16/09-11/17/09	Electro-Source Kanata (Ottawa) Ontario, CAN	1,200	12	Register
Fundamentals of FPGA Design	11/18/09-11/18/09	Electro-Source Kanata (Ottawa) Ontario, CAN	600	6	Register
Designing for Performance	11/19/09-11/20/09	Electro-Source Kanata (Ottawa) Ontario, CAN	1,300	13	Register
Designing with the PlanAhead Analysis and Design Tool	12/3/09-12/4/09	Electro-Source Kanata (Ottawa) Ontario, CAN	1,400	14	Register
Designing with the Virtex-6 Family	12/15/09-12/17/09	Electro-Source Kanata (Ottawa) Ontario, CAN	1,800	18	Register
Embedded Systems Development	1/19/10-1/20/10	Electro-Source Kanata (Ottawa) Ontario, CAN	1,400	14	Register
Designing with the Virtex-6 Family	1/21/10-1/22/10	Electro-Source Kanata (Ottawa) Ontario, CAN	1,400	14	Register
Designing with VHDL	2/2/10-2/4/10	Electro-Source Kanata (Ottawa) Ontario, CAN	1,800	18	Register
Minimizing Your Design Time with the ChipScope Pro Debug and Verification Tools	2/5/10-2/5/10	Electro-Source Kanata (Ottawa) Ontario, CAN	700	7	Register
Advanced VHDL	2/22/10-2/23/10	Electro-Source Kanata (Ottawa) Ontario, CAN	1,200	12	Register
For this location, please visit our ATP's website: Hardent

Oregon
For this location, please visit our ATP's website: Technically Speaking

Pennsylvania (Eastern)
For this location, please visit our ATP's website: Bottom Line Technologies

Pennsylvania (Western)
For this location, please visit our ATP's website: Vai Logic

Quebec, Canada
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Advanced VHDL	12/1/09-12/2/09	Hardent - Montreal, Quebec, CAN	1,200	12	Register
Embedded Systems Development	1/21/10-1/22/10	Hardent - Montreal, Quebec, CAN	1,400	14	Register
For this location, please visit our ATP's website: Hardent

Rhode Island
For this location, please visit our ATP's website: Hardent

Saskatchwan, Canada
For this location, please visit our ATP's website: Hardent

South Carolina
For this location, please visit our ATP's website: Hardent

South Dakota
For this location, please visit our ATP's website: North Pole Engineering

Tennessee
For this location, please visit our ATP's website: Hardent

Texas
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Embedded Systems Development	11/16/09-11/17/09	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Advanced Features and Techniques of Embedded Systems Development	11/18/09-11/19/09	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Designing with Multi-Gigabit Serial I/O	12/1/09-12/3/09	Xilinx Learning Center - Dallas, TX , USA (20)	1,800	18	Register
Designing with the PlanAhead Analysis and Design Tool	1/21/10-1/22/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Embedded Systems Development	1/26/10-1/27/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Advanced Features and Techniques of Embedded Systems Development	1/28/10-1/29/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Designing a LogiCORE PCI Express System	2/4/10-2/5/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Designing for Performance	2/11/10-2/12/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
DSP Design Using System Generator	2/18/10-2/19/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Designing with the Virtex-5 Family	2/24/10-2/24/10	Xilinx Learning Center - Dallas, TX , USA (20)	600	6	Register
Advanced FPGA Implementation	2/25/10-2/26/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
Designing with Multi-Gigabit Serial I/O	3/3/10-3/5/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,800	18	Register
Advanced VHDL	3/9/10-3/10/10	Xilinx Learning Center - Dallas, TX , USA (20)	1,200	12	Register
For this location, please visit our ATP's website: Faster Technology

Utah
Class Title	Date	Location / Facility	Price (USD)	Training Credit	Register
Designing with the Spartan-6 and Virtex-6 Families	12/8/09-12/10/09	Guru Labs - Bountiful - UT	1,500	15	Register
Signal Integrity and Board Design for Xilinx FPGAs	01/12/10-01/14/10	Guru Labs - Bountiful - UT	1,200	12	Register
No classes scheduled for the next 4 months in this location. Request a Private or Public Class

Virginia
For this location, please visit our ATP's website: Bottom Line Technologies

Vermont
For this location, please visit our ATP's website: Hardent

West Virgina
For this location, please visit our ATP's website: Vai Logic

Washington
For this location, please visit our ATP's website: Technically Speaking

Wisconsin
For this location, please visit our ATP's website: North Pole Engineering

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