Troubleshoot

Devices
Design Tools
Intellectual Property

Devices
Clocking	Clocking Debug Guide Diagnose and troubleshoot common issues with clocking Spartan®-3 Generation FPGA User Guide; Chapter 3 - Using DCMs (UG331) Debug issues with clock propagation, synthesis, and deskew
Configuration	Configuration Problem Solver Debug common configuration issues
CPLD	CPLD Problem Solver (XTP016) Debug problems with CPLD fitting
Fabric	Spartan-3 Generation FPGA User Guide; Chapter 5 - Using Block RAM (UG331) Learn and cross-check block RAM mode settings to debug read / write operations CPLD Problem Solver (XTP016) Debug problems with CPLD hardware
I/O Interfaces	Eliminating I/O Coupling Effects When Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs (XAPP459) Optimize I/O interface for large swing signals CPLD I/O User Guide (UG445) Learn the behaviour of the I/Os under various operating conditions Learn how to use the different termination modes, how to understand thresholds, loading effects the I/Os and powering considerations
Design Tools
Licensing	Xilinx Answer 32301 Troubleshooting Xilinx Software License Issues
Timing	Timing Constraints User Guide (UG612) Debug issues related to constraining your design and timing analysis Learn what constraints to use for your design
System Generator for DSP	System Generator for DSP User Guide; Chapter 1, "System Level Modeling in System Generator", and "Timing and Clocking" Hardware design using System Generator Xilinx Answer 31095 System Generator for DSP Internal/Fatal Errors Xilinx Answer 29595 System Generator for DSP Release Notes and Known issues
Intellectual Property
MAP	Xilinx Answer 23990 Master Answer Record for MAP Trimming issues Xilinx Answer 23363 Master Answer Record for MAP crashes Xilinx Answer 29711 Master Answer Record for debugging Pack:679 errors
All IP Cores	IP Release Notes Guide (XTP025) IP Core's Version history and links to their associated release notes
PCIe	Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE Designs for PCI Express (XAPP1002) Debug PCIe® design problems not caught in simulation using ChipScope™
Memory Interface Generator	Memory Interface Generator (MIG) User Guide; Section V, Chapter 13 - DDR2 Debug Guide (UG086) Debug problems encountered during Hardware testing of MIG Generated Interfaces Memory Interface Generator (MIG) User Guide (UG086) Learn how to properly modify a MIG Virtex®-5 DDR2 SDRAM pin-out using Update Design Debug any issues encountered with Virtex-5 DDR2 SDRAM pin-out modifications
Ethernet Cores	LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 User Guide; Appendix F - Debugging Guide (UG155) Debug issues encountered when using the PCS/PMA 1000BASE-X or SGMII Core LogiCORE IP XAUI User Guide; Appendix D - Debugging Guide (UG150) Debug designs that use XAUI core
SPI-4.2 (Dynamic Phase Alignment)	SPI-4.2 White Paper - Debugging DPA (WP249) Diagnose and fix design issues SPI4.2 Dynamic Phase Alignment