HDL Design using PlanAhead
XUP has developed tutorial and laboratory exercises for use with the XUP supported boards. The laboratory material is targeted for use in a introductory Digital Design course where professors want to include FPGA technology in the course to validate the learned principles through creating designs using ISE.
The tutorial is developed to get the users (students) introduced to the digital design flow in Xilinx programmable devices using PlanAhead design software suite. The laboratory exercises include fundamental HDL modeling principles and problem statements. Professors can assign the desired exercises provided in each laboratory document. They also can make a separate request to access the source codes for the laboratory exercises. Number of exercises provide enough material for a semester-long course, considering couple of weeks spent is mid-term and final exams during a semester.
Complete source deck for each of the exercises is available to the professors. Professors who are interested in obtaining the complete source deck, please send email to XUP stating the language (Verilog/VHDL) in the message body and providing complete title, email address, and the university address.
|Lab1 - Modeling Concepts||Lab1||Lab1||Lab1||Lab1|
|Lab2 - Numbering Systems||Lab2||Lab2||Lab2||Lab2|
|Lab3 - Multi-Output Circuits||Lab3||Lab3||Lab3||Lab3|
|Lab4 - Tasks, Functions, and Testbench||Lab4||Lab4||Lab4||Lab4|
|Lab5 - Modeling Latches and Flip-Flops||Lab5||Not required||Lab5||Not required|
|Lab6 - Modeling Registers and Counters||Lab6||Not required||Lab6||Not required|
|Lab7 - Behavioral Modeling and Timing Constraints||Lab7||Not required||Lab7||Not required|
|Lab8 - Architectural Wizard and IP Catalog||Lab8||Not required||Lab8||Not required|
|Lab9 - Counters, Timers, and Real-Time Clock||Lab9||Not required||Lab9||Not required|
|Lab10 - Finite State Machines||Lab10||Not required||Lab10||Not required|
|Lab11 - Sequential System Design using ASM Charts||Lab11||Not required||Lab11||Not required|