The ISE Design suite is the industry-proven solution for All Programmable devices including 7-Series, pre-7 series devices (Virtex-6, Spartan-6, Virtex-5, Virtex-4, Spartan-3x, Virtex-2P), and Zynq All Programmable SoC.
XUP has developed number of workshops using ISE Design suite. These workshops are typically two days long. All workshop materials are in English and consist of presentation slides and lab documents. Professors can freely re-use the presentation material in their classroom for teaching purpose. There is no restriction to add, modify or delete the slides giving professors complete control and flexibility to incorporate the material according to the course objectives.
The lab source files are available for the students to carry out the labs. Lab solutions are only available to the professors.
|FPGA Design Flow||Introductory||Atlys, Nexys3, XUPV5, Genesys, S3E Kit||13.x, 12.x|
|DSP Design Flow||Introductory||Atlys, XUPV5, S3E Kit||14.x, 13.x, 12.x|
|Embedded System Design Flow on Zynq||Introductory||ZedBoard||14.2|
|Embedded System Design Flow on MicroBlaze||Introductory||Atlys, Nexys3, XUPV5, Genesys, S3E Kit||14.2, 13.x, 12.x|
|High-Level Synthesis Flow on Zynq||Introductory||ZedBoard||14.2|
|High-Level Synthesis Flow on MicroBlaze||Introductory||Atlys||14.x, 13.x|
|Advanced Embedded System Design on Zynq||Intermediate||ZedBoard||14.4|
|DSP Primer||Intermediate||ZedBoard, Atlys||14.4|
|Embedded Linux on MicroBlaze||Intermediate||Atlys||14.2|
|Partial Reconfiguration Flow||Intermediate||ML605, XUPV5, Genesys||14.2, 13.x, 12.x|