UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

High-Level Synthesis Flow on MicroBlaze using ISE

Course Description This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS.
Level Introductory
Duration 2 Days
Who should attend? Professors who are familiar with Xilinx FPGA technology and wish to get up to speed with system design using high-level synthesis technique.
Pre-requisites
  • System level design experience using Xilinx FPGA
  • Basic experience with Xilinx ISE® Foundation™ and EDK software
  • Good understanding of C programming

Skills Gained

After completing this workshop, you will be able to:

  • Understand high-level synthesis flow of Vivado HLS
  • Apply directives to optimize design performance
  • Create a custom peripheral and add it to a processor system

Course Overview

Day 1:

  • Introduction to HLS with Vivado HLS
  • Demo: Power of Vivado HLS
    • View a demo of Vivado HLS generated core for a video application.
  • Using Vivado HLS
  • Lab 1: Creating Project and Understanding Reports
    • Experience a basic design flow of Vivado HLS and review generated output.
  • Improving Performance
  • Lab 2: Optimizing Performance through Pipelining
    • Use pipelining technique to improve performance.
  • Data Types

Day 2:

  • Optimizing for Area and Resources
  • Lab 3: Optimizing Area
    • Use directives to optimize resource sharing.
  • Handling Block and Port Level Protocols
  • Coding Style
  • Creating a Processor System
  • Lab 4: Designing an Audio System
    • Use pcore generation capability of Vivado HLS and integrate generated pcore in an embedded system developed using EDK.
Page Bookmarked