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HDL Design using Vivado

XUP has developed tutorial and laboratory exercises for use with the XUP supported boards. The laboratory material is targeted for use in a introductory Digital Design course where professors want to include FPGA technology in the course to validate the learned principles through creating designs using Vivado.

The tutorial is delevloped to get the users (students) introduced to the digital design flow in Xilinx All Programmable devices using Vivado design software suite. The laboratory exercises include fundamental HDL modeling principles and problem statements.  Professors can assign the desired exercises provided in each laboratory document.  They also can make a separate request to access the source codes for the laboratory exercises.  Number of exercises provide enough material for a semester-long course, considering couple of weeks spent in mid-term and final exams during a semester.

Complete source deck for each of the exercises is available to the professors.  Professors who are interested in obtaining the complete source deck, please send email to XUP stating the language (Verilog/VHDL) in the message body and providing complete title, email address, and the university address.

Supporting Material

Labs Material

  Verilog VHDL
  2015x 2013x 2015x 2013x
Title PDF Source PDF Source PDF Source PDF Source
Vivado Tutorial Tutorial Tutorial Tutorial Tutorial Tutorial Tutorial Tutorial Tutorial
Lab1 - Modeling Concepts Lab1 Lab1 Lab1 Lab1 Lab1 Lab1 Lab1 Lab1
Lab2 - Numbering Systems Lab2 Lab2 Lab2 Lab2 Lab2 Lab2 Lab2 Lab2
Lab3 - Multi-Output Circuits Lab3 Lab3 Lab3 Lab3 Lab3 Lab3 Lab3 Lab3
Lab4 - Tasks, Functions, and Testbench Lab4 Lab4 Lab4 Lab4 Lab4 Lab4 Lab4 Lab4
Lab5 - Modeling Latches and Flip-Flops Lab5 Lab5 Lab5 Not required Lab5 Lab5 Lab5 Not required
Lab6 - Modeling Registers and Counters Lab6 Not required Lab6 Not required Lab6 Not required Lab6 Not required
Lab7 - Behavioral Modeling and Timing Constraints Lab7 Not required Lab7 Not required Lab7 Not required Lab7 Not required
Lab8 - Architectural Wizard and IP Catalog Lab8 Not required Lab8 Not required Lab8 Not required Lab8 Not required
Lab9 - Counters, Timers, and Real-Time Clock Lab9 Not required Lab9 Not required Lab9 Not required Lab9 Not required
Lab10 - Finite State Machines Lab10 Not required Lab10 Not required Lab10 Not required Lab10 Not required
Lab11 - Sequential System Design using ASM Charts Lab11 Not required Lab11 Not required Lab11 Not required Lab11 Not required