Proving hardware interoperability is key to ensuring market acceptance of networking silicon because it confirms that the silicon device will work as expected with silicon devices from other silicon vendors. "Interoperability" implies" Plug and Play" operation. OEMs generally favor devices that have been tested for interoperability because they know that untested devices may cause product delays and increase the support burden.

Xilinx is the only programmable logic vendor to complete the Fibre Channel conformance and interoperability tests at the University of New Hampshire Interoperability Laboratory (UNH IOL) on its Fibre Channel LogiCORE™ IP. System designers building high performance networking equipment using the Xilinx® Fibre Channel solution can benefit from

• Reduced risk
• Accelerated time-to-market
• Proven interoperability with other standards compliant device(s)
• Significantly reduced hardware testing cycle
• Highest likelihood of first time design success and seamless plug-and-play operation
• Lowered support burden in the field

Test Setup for Fibre Channel LogiCORE IP Hardware Verification

The test setup which was used for hardware verification of the Fibre Channel LogiCORE IP is shown in Figure 1 below.

Figure 1. UNH IOL test setup for Fibre Channel core.

A simple Fibre Channel B Port design containing an instantiation of the Fibre Channel LogiCORE IP netlist was implemented on a Xilinx Virtex-II Pro XC2VP50 device residing on a Xilinx ML323 Characterization Board. The FC netlist was configured to support the Statistics gathering and Management Interface options.

iMPACT was used to create the B Port design configuration bitstream data for the XC2VP50 device. The bitstream was stored on a Compact Flash (CF) card. The configuration bitstream on the CF card in turn was used to program the XC2VP50 device. A download cable was used to connect the Chipscope™ Pro software running on the PC to the ML323 board.

Software developed in C running on the embedded PowerPC® 405 processor, together with the Statistics Gathering block in the core were used to implement the FC-FS Section 28 Speed Negotiation algorithm.The software controlled the speeds of the TX and RX paths following the given protocol and used link status statistics and built-in timers in the PPC405 to negotiate with third party equipment.

This setup was proven to negotiate correctly when connected to a QLogic 2 Gbps N Port and to a QLogic 1 Gbps Switch at UNH IOL.

UNH IOL Testing of the 1G/2G Fibre Channel LogiCORE IP

Xilinx completed testing of its Fibre Channel (FC) LogiCORE IP at the UNH IOL in April 2004. Testing was performed against the FC-PH standard for 1 Gbps and 2 Gbps operation.

The protocol conformance and interoperability testing included the following four test suites:

• 1G FC-PH
• 2G FC-PH
• 1G FC1
• 2G FCSW2
  

Copies of the test reports listed are available through your local Xilinx FAE. Additional details regarding the Fibre Channel solution and other Xilinx connectivity solutions can be found here.