PCI Express® is positioned as the industry's third-generation I/O technology. First generation was ISA, second generation being PCI, and the third generation, PCI Express. The PCI Express technology has been ratified by the PCI Special interest Group (PCI SIG).

This third-generation I/O technology is needed today since PCI-based shared, parallel-bus-signaling technology is approaching its practical performance limits; it is increasingly difficult to scale-up bandwidth just by increasing the number of signal lines. More signal lines mean difficult clock-to-data skew management, creating complex PCB layout rules that make cost-effective implementations in the FR4 (current copper PCB) technology difficult. In addition, increasing the number of signal lines also increases the power dissipation. PCI Express allows for very high available bandwidth per pin with the ability to cost-effectively scale towards the 12 GHz limits of copper signaling technology.

PCI Express is designed to be a general-purpose serial I/O interconnect that can be used in multiple market segments, including desktop, mobile, server, storage and embedded communications. PCI Express can be used as a peripheral device interconnect, a chip-to-chip interconnect, and a bridge to other interconnects like 1394b, USB2.0, InifiniBand™ and Ethernet. It can also be used in graphics chipsets for increased graphics bandwidth.

Key Features of PCI Express

• Compatible with the current PCI software model: There are no changes required to the current Operating Systems while maintaining platform configuration and device driver interfaces. Enables smooth integration within future system allowing for broad industry adoption.
• Serial architecture; Low-pin-count point-to-point connection (link): Does away with some of the limitations of parallel bus architectures by using embedded clock timing and differential signaling. The embedded clock lowers pin count (no separate control and clock pins are required) and makes data synchronization easier than in a parallel-based technology. Data can traverse a connector and cable scheme allowing flexible system partitioning. Serial technology enables unique and small form factors, reduces cost, simplifies board design and routing and reduces signal integrity issues. Point-to-point interconnect means no multiple hosts on same bus creating a bottleneck.
• Bandwidth scalability and frequency and/or interconnect width: Each link can be scalable up in bandwidth by creating wider lanes to match applications use, such as a wider graphics port in Desktop or multiple bus bridges (PCI Express-to-PCI-X, -Gigabit Ethernet or - InfiniBand) in server platforms. The spec defines interface widths of x1, x2, x4, x8, x12, x16 or x32 lanes.
• Embedded clock or CDR (Clock Data Recovery): Lowers pin counts, enables superior frequency scalability versus source synchronous clocking, and makes data synchronization easier.
• Layered architecture: The architecture consisting of the Software layer, Transaction Layer, Data Link Layer and Physical Layer. Layering enables scalability, modularity and design reuse.
• Packetized protocol: Time multiplexing versus circuit switching. This allows more than two-way communication at one time unlike circuit switching where only a two-way communications can occur. With packet based protocol there is no wasted bandwidth.
• Advanced features: Aggressive power management, QoS, isochrony, hot attach/detach and RAS.