28 Gb/s Serial Transceiver Technology

Virtex®-7 HT FPGAs -- World's First 28 Gb/s 3D Heterogeneous Devices

  • Unprecedented levels of integration for total power reduction
  • Highest performance devices delivering 2.78Tb/s of bandwidth

Highest Bandwidth Devices for Nx100G & 400G Wired Applications

With up to sixteen 28.05 Gb/s and seventy-two 13.1 Gb/s transceivers, the Virtex-7 HT devices have 4x the bandwidth of competing FPGAs and higher levels of integration compared to ASSPs. These devices deliver superior signal integrity with high logic capacity designed to meet the demands of Nx100 and 400G applications in the wired communications market.

    • Consolidate ASSP devices in to one FPGA with OTN, Ethernet MAC, Interlaken, gearbox and other IP cores
    • Integrate using industry’s only single chip dual gearbox solution

Direct Connectivity to CFP2 Modules

Virtex-7 HT FPGAs are designed to work with the latest CFP2 and future CFP4 optical modules using 4x25 Gb/s links. These utilize half the area, consume half the power and reduce the cost per bit compared to CFPs. Virtex-7 HT FPGAs can interface to more than four ASICs/NPUs and interface to as many as four CFP2 modules.

Heterogeneous Silicon for Low Jitter and Noise Isolation

Noise coupling reduction is required to enable high signal integrity 25-28.05 Gb/s transceivers. Xilinx’s industry-leading 3D SSI technology is used to isolate the digital logic fabric from the analog transceiver circuits in Virtex-7 HT devices.

  • Delivers a 5–10 dB reduction in noise coupling compared a monolithic die approach.
  • Provides optimal signal integrity to enable faster 28.05 Gb/s design closure while reducing board cost and improving productivity.

Systems Integration with Stacked Silicon Interconnect Technology

Xilinx’s Stacked Silicon Interconnect (SSI) technology delivers superior system integration and ultra-high capacity in an unprecedented number of 28 Gb/s and 13.1 Gb/s capable transceivers while enabling lower levels of system complexity and reduced BOM costs.

  • Combines enhanced Super Logic Region (SLR) FPGA die slices and 25-28.05 Gb/s transceivers on a passive silicon interposer to create a three dimensional (3D) die stack
  • Up to 870K logic cells offered in the largest Virtex-7 HT device

Support Information

Help is available through Xilinx Online Support. Open a webcase using the case description “GTZ/Gearbox Beta"