ISE Simulator (ISim)

ISE® Simulator provides a complete, full-featured HDL simulator integrated within ISE. HDL simulation now can be an even more fundamental step within your design flow with the tight integration of the ISE Simulator within your design environment.

ISE Simulator Key Features:

• VHDL-93 language support
• Verilog-2001 language support
• Mixed VHDL and Verilog simulation
• Tcl-based simulation console window
• Behavioral/RTL simulation prior to synthesis
• Timing simulation after place and route or fitting
• Design hierarchy, waveform, and console views
• Source-level debugging capabilities
• Command-line console features TCL interface
• Native support for all HardIP
  • PowerPC®, MGT, PCIe
• The ability to generate Synopsys Activity Interchange Files (SAIF) for use in Xilinx Power Optimization and Analyzer tools