What's New in the ISE® Design Suite 12.4 for DSP Designers

System Generator and CORE Generator

• System Generator performance improvements:
  • Improved simulation and net listing speed by 20% over the 12.3 release for large designs.
  • First time simulation initialization of models reduced by 15% to 35% compared to 12.3.
• Support for new FIR Compiler 6.1 with fractional rate support.
• MATLAB 2010b production support.
• Updated System Generator examples with AXI.

What's New in the ISE® Design Suite 12.3 for DSP Designers

Support for all 12.3 AXI-based designs is Pre-Production.

AXI4 IP Support in System Generator and CORE Generator (Pre-Production)

• Complex Multiplier 4.0
• DDS Compiler 5.0
• FFT 8.0
• FIR Compiler 6.0

Beta support for AXI Pcore Generation

• System Generator bus abstraction will allow existing designs to be ported over to AXI by just selecting a radio button on the EDK block in System Generator.

EDK design import of AXI systems

• AXI® based EDK designs can be imported and co-simulated using HW Co-simulation.

SDK Co-debug of AXI systems

• Software debug with SDK of AXI systems
• Pcore design and debug in System Generator
• Tutorial updated with AXI FIR and AXI Pcore

Decreased Run Time for the Entire Flow

• Includes a 2x-3x decrease in run time for the entire flow from design loading to netlisting in System Generator 12.3.
• Includes improvements in Compile (Ctrl-D), Initialization, Simulation and Netlisting steps.

What's New in the ISE Design Suite 12.2 for DSP Designers

System Generator Enhancements

System Generator 12.2 Performance Improvements

• When opening a typical model in System Generator 12.2, you will see models open
  about 2x faster the first time compared to System Generator 12.1. For additional
  viewing of the model, you will typically see a 10x improvement compared to System
  Generator 12.1.
• When opening System Generator blocks such as the FFT, FIR Compiler, and DDS
  Compiler in Release 12.2, you will see an average decrease in time of up to 30%
  compared to System Generator 12.1.
• When generating large designs for the first time, the netlisting time has been reduced
  by an average of 20% compared to System Generator 12.1.
  

Hardware Co-Simulation Improvements

• JTAG Co-simulation now supports a remote JTAG cable connection via the CSE
  (ChipScope Engine) server (which is also being used with iMPACT software and
  ChipScope Pro software). This allows you to run JTAG co-simulation over a JTAG cable
  that is connected to a board in a remote location.

MATLAB/Simulink Support

• Production support for MATLAB®/Simulink 2010a.
• Beta support for MATLAB/Simulink 2010b.

Xilinx Blockset Enhancements

Existing Block Updates

Reed Solomon Decoder 7.1

• Restored support for the Spartan®-6 device family.
  

Reed Solomon Encoder 7.1

• Restored support for the Spartan-6 device family.

What's New in the ISE Design Suite 12.1 for DSP Designers

System Generator Enhancements

New Operating System Support

• Native support for the following 64-bit operating systems has been added and allows System Generator to access the additional memory possible with 64-bit operating systems:
  • Windows XP 64-bit
  • Windows VISTA 64-bit SP1

Hardware Co-Simulation Improvements

• System Generator supports Ethernet Point-to-Point Hardware Co-Simulation for the Spartan-6 FPGA SP601 and SP605 Platforms
  • JTAG was already supported on these platforms, but the addition of Ethernet support enables more than an order of magnitude higher data transfer rates to and from the board
• System Generator provides support for more than one JTAG cable connect to the computer so that customers can have more than one hardware co-simulation token in a design
• System Generator provides support for custom JTAG cables, like the cable used to connect ChipScope™ for increased flexibility

Enhanced Integration with ChipScope

• A ChipScope block can be included in a JTAG Hardware Co-Simulation design to provide additional visibility during debug
• Repetitive-trigger data can be imported with the xlLoadChipScopeData utility function. Some situations require the repetivite-trigger mode to capture the necessary data during debug.

System Generator & Software Development Kit (SDK) Co-Debug (Beta Feature)

Xilinx ISE® Design Suite 12 includes a new beta feature that introduces key improvements in the integration flow between System Generator, Xilinx Platform Studio (XPS), and Software Development Kit (SDK). These improvements enable users to perform concurrent hardware and software co-debug on a MicroBlaze™ processor subsystem imported into System Generator..

The following are some of benefits of using Co-Debug between System Generator and SDK:

• Concurrent visibility of software and hardware for debug
  • Set a breakpoint and debug while the MicroBlaze and hardware are stopped
  • Signals to probe do not need to be chosen before the bit stream is generated
• Find a bug, modify the C code, recompile and update the bitstream in seconds
  • No need to rerun synthesis and the implementation flow when the software changes
• Tight integration
  • The SDK project is automatically set up with the correct hardware platform
  • The required logic is automatically added to the design

Existing Block Updates

DSP48 Macro 2.0

• Fixed the simulation of the DSP48 Macro when it is configured with zero latency i.e. the block has a combinatorial path from input to output.

FIR Compiler 5.0

• Fixed the issue with incorrect output binary point for dout port when rounding is being used for the output.
• Fixed the issue with incorrect settings being saved on the block if the coefficient vector was not defined.
• Removed the restriction on non-availability of Symmetric Rounding Options for Virtex®-5 and Virtex-6 device family

Fast Fourier Transform 7.0

• Removed support for Spartan-6 device family. Use Fast Fourier Transform 7.1 block for Spartan-6 devices.
• This block has been superseded by Fast Fourier transform 7.1 block

Fast Fourier Transform 7.1

• Support added for Virtex-6 Q, Spartan-6, Spartan-6Q, Spartan-6 Low Power.
  Note: This block supersedes the Fast Fourier Transform 7.0 block. The Fast Fourier Transform 7.1 block addresses the Spartan-6 9K Block RAM Simple Dual Port (SDP) Data Width Restriction as described in Answer Record 34541

Reed Solomon Decoder 7.0

• Removed support for Spartan-6 device family.

Reed Solomon Encoder 7.0

• Removed support for Spartan-6 device family.

CIC Compiler 2.0

• Support for Virtex®-6Q and Spartan-6Q FPGAs
• Supports Automatic Update from CIC Compiler v1.1, v1.2 and v1.3
  Note: This block supersedes the CIC Compiler 1.3 block.

Interleaver Deinterleaver 6.0

• Support for Virtex-6, Virtex-6Q Virtex-6 Low Power, Spartan-6, Spartan-6Q, Spartan-6 Low Power
  Note: This block supersedes the Interleaver/De-interleaver 5.1 block.

Convert

• An enable port has been added to the block interface.