Introducing the ISE® Design Suite: DSP Edition. The ISE Design Suite: DSP Edition provides DSP development tools and IP tailored to the needs of algorithm, system, and hardware developers in addition to the base level FPGA design tools and technologies. The ISE Design Suite: DSP Edition includes the following products:
The ISE Design Suite DSP Edition supports the base methodology required for the DSP Domain Targeted Design Platform.
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This latest release of the ISE Design Suite provides support for the new Virtex-6 HXT FPGA platform delivering the industry's highest bandwidth FPGA with up to 72 serial transceivers for high-bandwidth applications such as bridging, switching, and aggregation, in wired telecommunications and data communications systems.
For details on enhancements specific to logic design available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.
System Generator for DSP provides support for the following new devices:
Note: This block supersedes the DDS Compiler 3.0 block. DDS Compiler version 4.0 is not bit-accurate with respect to earlier versions. Also, latency of phase offset effects has been balanced with the latency of phase increments for ease of use in the streaming modes. This change also applies to existing programmable and fixed modes.
Note: This block supersedes the CIC Compiler 1.2 block. The RATE_WE signal no longer acts as a reset to the core; the core will update to the new rate on the next input sample (for a single channel implementation) or the next input to the first channel (for multiple channel implementations).
Experience a complete software flow for the new Virtex®-6 and Spartan®-6 targeted design platforms. All Editions of the ISE Design Suite include new features specifically added to enhance Virtex-6 and Spartan-6 performance. For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.
All ISE Design Suite products and select Xilinx IP are now licensed using FLEXnet Publisher from Acresso Software Inc. The incorporation of this EDA industry standard licensing solution allows greater flexibility for ISE Design Suite Users.
Products can now be licensed in different ways to best suit a users needs:
Xilinx has simplified the process of obtaining and licensing software, allowing you to download and license Xilinx software and most other FLEXnet licensed Xilinx IP products from a single website. Customer license or CAD-tool administrators now have improved ability to manage Xilinx software and IP licenses from a single web-location IP licensing procedures now merged with software licensing flow. This will greatly reduce the time it takes to obtain an IP license to just a few hours, or even minutes, in some cases.
System Generator for DSP now provides support for Red Hat Enterprise Linux 4 WS (32 and 64 bit). This new support enables enterprise deployment for customers who want to have design tools easily available from centralized servers. Customers targeting larger FPGA devices with System Generator now have a way to access more memory via a 64 bit operating system.
Both System Generator for DSP and the AccelDSP synthesis tool now provide support for MATLAB R2008b.
Greater integration between System Generator for DSP and the Software Developers Kit (SDK) enables algorithm developers to use the software development environment of SDK for the embedded portion of their design which will run on the embedded processor.
AccelDSP can now leverage LogiCORE™ from Core Generator during VHDL generation where each operator is optimized for the target device. This process guarantees mapping to the desired hardware resources while designing at a higher level of abstraction. This results in higher performance (up to 2x with an average of 77% across an array of designs) and lower area operators.
To more easily leverage the LogiCORE integration, new AccelDSP synthesis tool reports show the user where the largest operators are in the design. For example, the user might notice there is a 40 bit by 40 bit multiplier in the design. If he can modify the algorithm so that 18 bits by 18 bits will still meet his fidelity, the user will be able to reduce the area and increase the performance of their design.