AXI-based design support moves to production status for all embedded tools and IP..

Base System Builder supports single processor AXI systems
- Dual processor system support coming
System Assembly View support for AXI Interconnect models
- includes representation of sparse interconnect connectivity
- interconnect configuration dialogs
- support cascading of multiple AXI interconnect IPs
Auto-connection of AXI slave modules in System Assembly View
- includes bus interface, clock and I/O connections
- automatic address assignment
Auto-bus connection expanded to support addition of MicroBlaze in System Assembly View
- auto-inference of MicroBlaze cache memory, AXI4-Lite peripheral bus, and inclusion of BRAM memory
Simplified connections of AXI IP outside of embedded subsystem
Support for separate clock domains for AXI master and slave IP
- clock conversion logic handled automatically
Support for AXI ChipScope monitors
Streamlined integration of Memory Interface Generator flows for AXI-based DDR interfaces
Order of IP in System Assembly View can be customized by user
Enhancements to Ports View in System Assembly View

MicroBlaze v8.10.a little endian support (AXI only)
- Updated GNU tool chain, including new –mlittle-endian switch
- Updated software tools, including XMD, Libgen, and Flashwriter
System Generator co-debug enabled for AXI IP
Drivers and BSP support for AXI IP
Sample applications generated for AXI IP
Xilkernel support for AXI designs
Support for MDM v2.00.b in AXI mode

Support for all 12.3 AXI-based designs is Pre-Production.

Support for AXI based designs (pre-production)
- Base System Builder support for single MicroBlaze AXI based designs.
- Ability to stitch together a system with AXI based IP interfaces.
- Each AXI master or slave can run at a different frequency. XPS automatically handles any clock conversion logic that is needed.
- XPS System Assembly View Connectivity panel provides mechanism to capture sparse connectivity between various AXI masters and slaves for AXI Interconnect IP.
- AXI Interconnect IP Configuration Gui Dialog to change Master/Slave specific setting.
- Automatic connection of an AXI Slave module at the time of instantiation in System Assembly View. This includes bus interface, clock and IO connections, and automatic address assignment.
- Support for embedded software development is not available in XPS for AXI based designs. SDK is the primary embedded software development tool. XPS continues to support software development for PLB designs in a deprecated mode.
- Streamlined integration of MIG flows for AXI based DDR interfaces.
- AXI Chipscope Monitor support.
- Ability to cascade multiple AXI interconnect IP blocks in a system.
XPS Ports View now shows ports grouped as being part of a Bus or an IO Interface. Ability to easily connect ports of an interface to modules outside EDK sub-system.
Users can re-arrange the order in which IP blocks are shown in the System Assembly View and customize the view suitable to their design.

Support for pre-production AXI-based designs
- MicroBlaze v8.00a little-endian support (AXI only)
  - GNU tool chain updated, including new –m little-endian switch
  - Make file generation
  - Software tool updates, including SDK, XMD, Libgen, and FlashWriter
- System Generator co-debug enabled for AXI IP
- Drivers and BSP support for AXI IP
- Sample application generation for AXI IP
- Xilkernel support for AXI IP
- MDM v2.00a with AXI interface available
User interface updates
- Relative paths for repositories are allowed if the repository is at the same directory level as the BSP directory or one level above.
- Repository paths are refreshed when importing BSP projects.
- Manual modification of BSP settings file (MSS) now triggers a rebuild.
- Restoring defaults in C/C++ build settings no longer removes inferred options.
- Default suggested Windows workspace location changed.
Sample applications
- Hello World SDK sample application supports MDM UART
Documentation update
- Screencast demonstrating how to use SDK available from the SDK Welcome page
Bug corrections
- Includes patches provided with 12.3 Answer Record 36777

Over 30 new AXI-based Embedded Edition peripheral IP cores in pre-production
Minor enhancements to six PLB-based Embedded Edition IP cores
New AXI Ethernet core featuring three fee-based licensed configuration modes
- Full TEMAC, 10-100 only, and optional AVB (Audio-Video Bridging)

IP Configuration Dialogs open automatically when IP Is added in the System Assembly View
New filters in Ports view – Clock only, Reset only, Interrupt only
New filters in Bus Interface View to filter out specific types of point to point connections

Can now download very large .elf files
New project wizard will now successfully create BSP when the only STDIN/STDOUT device is the JTAG UART
Enhanced assistance for upgrading projects from older versions of SDK
New version 7.30.b – bug fixes and quality performance enhancements

For details on enhancements specific to logic design available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.

Support for ISIM Simulator – simulate embedded designs using the included ISE HDL simulator
NT64 Support – native Windows NT 64-bit support
Ability to “Export Hardware Design to SDK” from ISE Project Navigator – fast, transparent setup of hardware definitions for software design
Simplified Project Options Dialog – easier startup of embedded projects
New Cygwin version - supports multiple installations of Cygwin to exist on one system

Upgraded to Latest Eclipse Version (v3.5.1) – delivers all the most recent Eclipse standards
Updated to Latest CDT (C/C++ Development Tools) Release (v6.0.1) – utilize the industry’s latest C/C++ software design support
Simplified Flows for Creating Initial C Application – get through your software design flow faster

New Configuration Wizard – multiple starting MicroBlaze preconfiguration options, guides you through processor setup
Branch Target Buffer – stores recently taken branch locations speeding up future execution
Branch Prediction - keeps the instruction pipeline full, maximizing processor performance
Victim Cache – stores recently flushed cache lines locally for faster processing

Spartan-6 and Virtex®-6 production support (except MPMC Virtex-6 remains pre-production) – design to the newest Xilinx FPGA devices
PLBv34 and OPB-based cores have been removed – faster download and smaller IP install footprint
New IP Support Terminology – standard IP terminology across all Xilinx cores
Minor core updates (see individual core logs for details)

For details on enhancements specific to logic design available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.