What's New in the ISE® Design Suite 12.4 for Intellectual Property
The 12.4 Release builds on 12.3 and adds Production support for AXI IP for 12.4 AXI-based designs.
For more information see www.xilinx.com/ipcenter/coregen/updates_12_4.htm
What's New in the ISE® Design Suite 12.3 for Intellectual Property
Support for all 12.3 AXI-based designs is Pre-Production.
Introducing CORE Generator IP with AXI4 Interface
- The latest versions of the following CORE Generator™ IP have been updated with AXI4 interface support
- Connectivity IP
- Aurora 8B/10B v6.1
- Now available with AXI4-Stream Interface
- Performance capabilities are retained from the LocalLink version and core size increases are minimal
- CAN v4.1 - Now available with AXI4-Lite interface
- DisplayPort v2.1 - Now available with AXI4-Lite interface
- PCI Express
- Spartan®-6 and Virtex®-6 Integrated Block for PCI Expres® v2.1 available with the AXI4-Stream interface
- The core retains the performance capabilities of the TRN version with minimal increase in core size
- DSP IP
- FIR Compiler v6.0, DDS Compiler v5.0, Complex Multiplier v4.0, Fast Fourier Transform (FFT) v8.0
- Now available with AXI4-Stream interface
- Provides demonstration VHDL testbench for the selected core configuration
- Supports core upgrade from the previous version with legacy interface. Please note that this upgrade will only upgrade core parameters. The core instantiation in the design must be adapted to use the AXI4-Stream interface. For further information, please refer to the section on migrating from earlier versions in the respective IP data sheet.
- Memory and Storage Elements
- FIFO Generator v7.2
- Now available with AXI4, AXI4-Lite, AXI4-Stream and native interface
- Automatically uses Write First mode for Spartan-6 SDP BRAM-based FIFO configurations when different clocks are used for reduced BRAM utilization
- MIG v3.6 - Now available with AXI4 and native interface
- Wireless IP
- Introducing 3GPP LTE Channel Estimator v1.0
- Available with AXI4-Stream Interface
- The latest component of Xilinx's LTE Baseband Targeted Design Platform provides an optimized channel estimation function for the Physical Uplink Shared Channel (PUSCH) in LTE base stations. Antenna configurations up to and including 2x2 Multi-User MIMO are supported. Tailor this configurable function to meet the unique needs of your application.
- In general, the AXI4 interface will be supported by the latest version of an IP, for Virtex-6 and Spartan-6 device families. Older “Production” versions of IP will continue to support the legacy interface for the respective core on Virtex-6, Spartan-6, Virtex-5, Virtex-4 and Spartan-3 device families.
- For general information on Xilinx AXI4 support see www.xilinx.com/ipcenter/axi4.htm
- For more information on Xilinx AXI4 IP support see www.xilinx.com/ipcenter
Additional IP Highlights
- Digital Pre-Distortion (DPD) v3.0
- First release in CORE Generator
- This market leading DPD solution for common wireless standards reduces base station equipment CapEx and OpEx by increasing Power Amplifier efficiency. Configurable to support different algorithmic performance and area combinations, it allows customers to uniquely tune the core implementation to their needs. Supporting up to 8 antennas, it offers customers the smallest, lowest power and lowest cost FPGA based DPD solution available in the market today.
- Soft Error Mitigation (SEM) v1.1
- Automatically detects and corrects soft errors caused by ionizing radiation to enable highest system reliability and availability and reduce system costs.
- Configurable to support multiple error correction methods and includes optional error classification and error injection.
- Supports Xilinx Virtex-6 FPGA family and delivered in CORE Generator.
- Block Memory Generator v4.3
- New Write First mode support for Single Dual Port (SDP) memory type has been added for Spartan-6 devices. Use Write First mode instead of Read First for SDP BRAM when the Read and Write ports are clocked by different clocks to avoid address space overlap issues.
- Support for Soft Hamming Error Correction in SDP BRAM configurations for data widths < 64 bits (Virtex-6, Virtex-5, and Spartan-6 devices only).
- A comprehensive listing of cores that have been updated in this release can be viewed at www.xilinx.com/ipcenter/coregen/updates_12_3.htm in the IP in this Release tab
- For more information see www.xilinx.com/ipcenter/coregen/updates_12_3.htm
CORE Generator Enhancements
- A new “AXI4” column in the CORE Generator IP catalog highlights IP cores with AXI4 support.
- Information on supported AXI4 and native interfaces is displayed in the IP information panel.
- IP symbol can be expanded to display the components and their bit allocation on a single Tdata channel. For example: Complex Multiplier s_axis_a_tdata [31:0] pin symbol can be expanded to show packing of real[15:0] and imaginary[31:16] components.
- Access supplementary IP documents from the “Documents” pull down in the IP GUI as well as the IP information panel.
PlanAhead IP Design Flow Enhancements
- A new “AXI4” column in the IP catalog highlights IP cores with AXI4 support.
- Information on supported AXI4 and native interfaces is displayed in the IP details panel.
What's New in the ISE® Design Suite 12.2 for Intellectual Property
New IP Cores
SGMII over LVDS
- Provides designers with a GMII to SGMII bridge function using LVDS (SelectIO™ technology) instead of transceivers for chip-to-chip applications on Virtex-6 family devices. This new feature is an addition to the Ethernet 1000BASE-X PCS/PMA or SGMII IP LogiCORE™ IP v10.5. The core is included at no additional charge with the ISE Design Suite software
Wireless IP
- DUC/DDC Compiler
- Implements high-performance, optimized Digital Up and Down-Converter modules for use in wireless base stations and other suitable applications. In addition to a wide range of parameter options, resource trade-off options are available to enable you to tailor the core to specific design requirements
- 3GPP LTE Fast Fourier Transform (LTE-FFT)
- Implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidth support
PlanAhead IP Design Flow Enhancements
- Reduced IP customization GUI launch time
- Access to IP version information and answer records has been added. For fee-based IP, access to product pages has also been added
CORE Generator Enhancements
- Reduced CORE Generator application startup time
IP Updates - Highlights
- Memory IP
- Block Memory Generator v4.2
- New Write First mode support has been added for Single Dual Port (SDP) memory type (Virtex-6 only). Use Write First mode instead of Read First for SDP BRAM when the Read and Write ports are clocked by different clocks to avoid address space overlap issue without increasing BRAM usage
- Support for Soft hamming Error correction in SDP BRAM configurations for data widths < 64 bits (Virtex-6, Virtex-5, and Spartan-6 only)
- FIFO Generator v6.2
- Updated to support Write First mode for SDP BRAM-based FIFO configurations when the Read and Write ports are clocked by different clocks. Allows you to avoid address space overlap issues without increasing BRAM utilization
- FPGA Features and Design
- SelectIO Interface Wizard v1.4
- Added support for Virtex-6 FPGAs
- Video IP
- A comprehensive listing of cores that have been updated in this release can be viewed at http://www.xilinx.com/ipcenter/coregen/updates_12_2.htm
What's New in the ISE Design Suite 12.1 for Intellectual Property
Introducing new PlanAhead IP design flow
- The CORE Generator IP catalog can now be directly accessed from within PlanAhead.
- Get instant access to information on supported devices, IP version, life cycle status, datasheet and licensing information
- Integrate IP into your designs faster with IP instantiation templates that are generated immediately. IP elaboration is completed later in the design flow during the design synthesis stage.
For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.
Documentation
IP Release Notes Guide
Describes additions, updates, and known issues related to the Xilinx CORE Generator and IP Cores
New IP Cores
Video and Image Processing
- Image Characterization v1.0 - Calculates important statistical data for video input streams. Characterization is an important processing block for many applications including face recognition, object detection, and more.
Wireless IP
- 3GPP LTE RACH Detector v1.0 - Provides designers with an LTE RACH Detecting block, which decodes P-RACH data encoded according the the 3GPP TS 36.211 v8.6.0, Physical Channels and Modulation specification.
New CORE Generator Features
- Enhanced assistance with design migration
- Improved messaging for cores and core versions that have been removed from 12.1. A new warning message advises users about newer IP versions that are available along with additional information on core versions in the current project that can be automatically upgraded
- Project IP panel enhanced to display missing IP as "Upgradable", "Removed" or "Unavailable".
- IP catalog enhancements
- IP core now displays life cycle status of "Pre-Production" and "Production" on a per family basis.
- Automated core upgrade to latest version capability has been added for the following IP cores:
- Block Memory Generator v4.1
- CIC Compiler v2.0
- Clocking Wizard v1.5
- Fast Fourier Transform v7.1
- FIFO Generator v6.1
- SelectIO Interface Wizard v1.3
- System Monitor Wizard v2.0
IP Core Updates
What's New in the ISE Design Suite 11.5 for Intellectual Property
Documentation
IP Release Notes Guide
Describes additions, updates, and known issues related to the Xilinx CORE Generator and IP Cores
What's New in IP Cores in the ISE Design Suite 11.5
This release is a required update for all designs targeting Virtex-6 and containing the following IP cores:
- 10 Gigabit Ethernet MAC
- Aurora 64B/66B
- Aurora 8B/10B
- Block Memory Generator
- Clocking Wizard
- CPRI
- Ethernet 1000BASE-X PCS/PMA or SGMII
- FIFO Generator
- OBSAI
- RapidIO Logical (I/O) and Transport Layer Interface Core
- rapidIO Physical Layer Interface Core
- RXAUI
- Serial RapidIO
- SPI-3 Link Layer
- SPI-4.2
- SPI-4.2 Lite
- Tri-Mode Ethernet MAC
- Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper
- Virtex-6 GTX Wizard
- Virtex-6 Integrated Block for PCI Express
- XAUI
It is also a required update for all designs targeting Spartan-6 and containing the following IP cores:
- RapidIO Logical (I/O) and Transport Layer Interface Core
- RapidIO Physical Layer Interface Core
- SPI-4.2 Lite
- Tri-Mode Ethernet MAC
Note: For the listed cores, you will need to regenerate these cores and re-integrate them into your design.
What's New in the ISE Design Suite 11.4 for Intellectual Property
Documentation
IP Release Notes Guide
Describes additions, updates, and known issues related to the Xilinx CORE Generator and IP Cores
New IP Cores
Connectivity IP
- 10 Gigabit Ethernet PCS/PMA (10GBASE-R): Full-rate serial interface for 10 Gigabit Ethernet MAC
- DisplayPort: New serial protocol for high bandwidth Broadcast, Medical, and Consumer Display applications supporting transmission rates up to 2.75 Gbps
- Virtex-6 FPGA GTH Transceiver Wizard: New OTU-1, OTU-4, OC-48 and OC-192 protocol templates
- Spartan-6 FPGA GTP Transceiver Wizard: New XAUI protocol template
DSP IP
- DSP48 Macro: An easy to use graphical user interface which abstracts the XtremeDSP Slice configuration and simplifies its dynamic operation via a set of user defined mathematical expressions
Video IP
- Image Edge Enhancement: A fast and easy to use hardware block for enhancing the edges within a video image frame
- Image Noise Reduction: An easy to use image processing block for reducing noise within single or multiple image frames
- Image Statistics Engine: Performs hardware image analysis to support automatic focus, exposure, and white balance
- Motion Adaptive Noise Reduction: A high quality and easily configurable motion adaptive noise reduction function for integration within a wide variety of imaging applications
Wireless IP
- 3GPP LTE MIMO Decoder: Resource optimized and scalable MIMO decode function for 3GPP-LTE basestations
- Peak Cancellation Crest Factor Reduction (PC-CFR): Highly optimized and flexible CFR solution for cellular basestations
What's New in the ISE Design Suite 11.3 for Intellectual Property
Support for the Virtex-6 HXT FPGA Platform
This latest release of the ISE® Design Suite provides support for the new Virtex®-6 HXT FPGA platform delivering the industry's highest bandwidth FPGA with up to 72 serial transceivers for high-bandwidth applications such as bridging, switching, and aggregation, in wired telecommunications and data communications systems.
For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.
Documentation
IP Release Notes Guide
Describes additions, updates, and known issues related to the Xilinx CORE Generator and IP Cores
New IP Cores
FPGA Features and Design
- Spartan®-6 SelectIO Interface Wizard v1.1 - Generates an HDL file that contains IO logic such as IOSERDES and IODELAY blocks customized to the user's interface requirements.
- Virtex-6 FPGA GTH Transceiver Wizard v1.1 - Generates a custom wrapper that configures one or more Virtex-6 FPGA GTH transceivers according to user requirements. In addition, it produces an example design, testbench, and scripts to allow you to observe the transceivers operating under simulation and in hardware.
Video and Image Processing
- Video On Screen Display v1.0 - A sophisticated module that provides three hardware accelerated functions including multiple alpha blending layer compositor, simplified graphics processing unit (boxes), and simplified text processing unit for video systems.
- Video Direct Memory Access v1.0 - Allows Video Cores to access external memory via the Video Frame Buffer Controller (VFBC) within the Multiport Memory Controller under control of the host processor.
Communication and Networking
- RXAUI v1.1 - The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE IP provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2005. The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2005 clause 45 management registers.
Enhancements to the CORE Generator
- The CORE Generator now checks for IP license availability before proceeding through the process of core generation.
- Automated core upgrade to latest version capability has been added for the following IP cores:
- CIC Compiler v1.3
- DDS Compiler v4.0
- Distributed Memory v4.2
- Multiplier Generator v11.2
IP Core Updates
What's New in the ISE Design Suite 11.2 for Intellectual Property
Introducing Virtex-6 and Spartan-6 Device Support
Experience a complete software flow for the new Virtex-6 and Spartan-6 targeted design platforms. All Editions of the ISE Design Suite include new features specifically added to enhance Virtex-6 and Spartan-6 performance. For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.
Documentation
IP Release Notes Guide
Describes additions, updates, and known issues related to the Xilinx CORE Generator and IP Cores
New IP Cores
Video Timing Controller
A general purpose video timing detector and generator, which automatically detects blanking and active data timing based on the input horizontal and vertical synchronization pulses
Spartan-6 FPGA Integrated Endpoint Block for PCI Express
A Spartan-6 FPGA Endpoint solution for PCI Express to configure the Spartan-6 FPGA Integrated Endpoint Block for PCIe® FPGA and includes additional logic to create a complete Endpoint solution for PCIe
Virtex-6 Integrated Block for
PCI Express
Virtex-6 FPGA Endpoint solutions for PCI Express to configure the Virtex-6 FPGA Integrated Block for PCIe FPGA and includes additional logic to create a complete solution for PCIe
Virtex-6 Embedded Tri-mode
Ethernet MAC Wrapper
Automates the generation of HDL wrapper files for the embedded Tri-mode Ethernet MAC in Virtex-6 devices. Preconfigured HDL wrappers as well as testbenches and implement and simulation scripts are generated automatically based on user defined options.
Spartan-6 FPGA GTP Transceiver Wizard
Produces a wrapper that instantiates one or more properly configured
GTP transceivers for custom applications
Virtex-6 FPGA GTX Transceiver Wizard
Produces a wrapper that instantiates one or more properly configured
GTX transceivers for custom applications
Clock Wizard
Creates HDL source code for a clock circuit customized for your clocking requirements