What's New in the ISE Design Suite 11.3 for Intellectual Property

Support for the Virtex-6 HXT FPGA Platform

This latest release of the ISE® Design Suite provides support for the new Virtex®-6 HXT FPGA platform delivering the industry's highest bandwidth FPGA with up to 72 serial transceivers for high-bandwidth applications such as bridging, switching, and aggregation, in wired telecommunications and data communications systems.

For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.

Documentation

IP Release Notes Guide

Describes additions, updates, and known issues related to the Xilinx CORE Generator™ and IP Cores

New IP Cores

FPGA Features and Design

• Spartan®-6 SelectIO™ Interface Wizard v1.1 - Generates an HDL file that contains IO logic such as IOSERDES and IODELAY blocks customized to the user's interface requirements.
• Virtex-6 FPGA GTH Transceiver Wizard v1.1 - Generates a custom wrapper that configures one or more Virtex-6 FPGA GTH transceivers according to user requirements. In addition, it produces an example design, testbench, and scripts to allow you to observe the transceivers operating under simulation and in hardware.

Video and Image Processing

• Video On Screen Display v1.0 - A sophisticated module that provides three hardware accelerated functions including multiple alpha blending layer compositor, simplified graphics processing unit (boxes), and simplified text processing unit for video systems.
• Video Direct Memory Access v1.0 - Allows Video Cores to access external memory via the Video Frame Buffer Controller (VFBC) within the Multiport Memory Controller under control of the host processor.

Communication and Networking 

• RXAUI v1.1 - The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE™ IP provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2005. The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2005 clause 45 management registers.

Enhancements to the CORE Generator

• The CORE Generator now checks for IP license availability before proceeding through the process of core generation.
• Automated core upgrade to latest version capability has been added for the following IP cores:
  • CIC Compiler v1.3
  • DDS Compiler v4.0
  • Distributed Memory v4.2
  • Multiplier Generator v11.2

IP Core Updates

• Support for Virtex-6 HXT, Virtex-6 Lower Power, and Virtex-5Q have been added to selected cores in this release.
• A comprehensive listing of cores in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_3_datasheets.htm.
• For more information see www.xilinx.com/ipcenter/coregen/updates_11_3.htm

What's New in the ISE Design Suite 11.2 for Intellectual Property

Introducing Virtex-6 and Spartan-6 Device Support

Experience a complete software flow for the new Virtex®-6 and Spartan®-6 targeted design platforms.  All Editions of the ISE Design Suite include new features specifically added to enhance Virtex-6 and Spartan-6 performance. For details on enhancements available in all Editions, visit the "What's New" area of the ISE Design Suite: Logic Edition.