What's New in the ISE® Design Suite 12.4 for Logic Designers

ModelSim Xilinx Edition

• ModelSim Xilinx Edition-III is no longer released with the Xilinx ISE Design Suite. For more information, please see change notice XCN 10028 on Xilinx.com.

ISE Simulator

Project Navigator

• TBD

ChipScope Pro

• ChipScope IBERT for Virtex®-6 GTH parameter sweep support.
• ChipScope AXI monitor for AXI4-Stream in XPS
  • Supports AXI4-based designs for Spartan®-6 and Virtex-6 families.
  • Supports AXI4-Stream interface.

Implementation (Place and Route)

• New register ordering option to control slice register packing for buses (only for Spartan-6 and Virtex-6 FPGAs).

What's New in the ISE Design Suite 12.3 for Logic Designers

ModelSim Xilinx Edition

• 12.3 is the final release of Modelsim Xilinx Edition-III.  For more information, please see change notice XCN 10028 on Xilinx.com.

Project Navigator

• SmartXplorer Integration Improvements:
  • Support for custom SmartXplorer strategy files from within Project Navigator.
  • Ability to save only "N" best results in order to efficiently manage disk space.
  • Additional resource utilization data displayed in SmartXplorer Results window.
  • Ability to abort individual SmartXplorer runs.
• Project Archive Ability to Archive Sources Only:
  • New option to exclude generated files when creating a project archive.
• VHDL Library Creation Based on Directory of Files:
  • When creating VHDL Libraries, new option to create library based on file directory name and to automatically add all VHDL files from selected directory.

PlanAhead

PlanAhead now delivers a seamless “push-button” flow, as well as an advanced visualization and analysis flow. The PlanAhead tool’s cockpit also includes Project Management, Synthesis, CORE Generator integration, Floorplanning, Place-and-Route, ChipScope Pro tool integration and Bitstream generation. The entire Xilinx IP catalog, including AXI4 IP cores, is directly accessible and searchable from the same design cockpit.

• Device support update to include new Spartan-6 -3 speedgrades.
• Updated AXI IP core visibility in the IP Catalog and integration with CORE Generator.
• Pin Planning usability improvements, including table-based constraint editing, package pin location swaps, and improved visibility of configuration settings.
• Improved SSN prediction for Spartan-6 devices.
• Project infrastructure improvements
  • Ability to launch runs without unnecessary copying of sources.
  • Improvements to functionality for when directory trees added as sources.
  • Manual file ordering control for synthesis.
  • Backups to journal and log files.
  • Passing PCF files to bitgen.
  • Copy run feature.
• Added and improved Design Rule Checks.
• GUI improvements and changes
  • Removed on-the-fly creation of user-defined attributes.
  • Additional options for find-in-files.
  • Open project directly from the Getting Started page.
  • UCF file order display.
  • Ability to open a file browser in a run directory.
  • Improved identification of read-only files.
  • Tool tips for missing files.
  • Option to clear all output from the Tcl console view.
• Floorplanning improvements for swapping macro location constraints for block RAMs and DSPs.
• Improvements to ChipScope integration, for CDC file export and more consistent debug core naming convention.
• Added a new tutorial for Tcl and SDC commands.

ChipScope Pro

• Device support for IBERT Support
  • IBERT CORE Generator for Virtex-6 GTH rev2.0.
  • Analyzer IBERT Console for Virtex-6 GTH rev2.0
  • Example file for IBERT CORE Generator GUI panels for Virtex-6 GTX to show customers how to include IBERT core logic into their designs.
• ChipScope AXI monitor in XPS:
  • Supports AXI4-based designs for Spartan-6 and Virtex-6 families.
  • Supports AXI4-Memory Map and AXI4-Lite interfaces.

Implementation (Place and Route)

• Intelligent clock gating now supported for Spartan-6 FPGAs (including BRAM optimizations).

What's New in the ISE Design Suite 12.2 for Logic Designers

Project Navigator

• SmartXplorer:
  • Consistent use of TRCE options between Project Navigator and SmartXplorer.
  • Ability to perform Power Analysis with SmartXplorer runs.
  • Additional resource utilization data displayed in SmartXplorer Results viewer.
  • Ability to customize displayed data in SmartXplorer Results viewer.
  • Ability to compare multiple SmartXplorer runs.
  • Ability to specify maximum number of runs to save.
• ISE® Design Summary and Report Viewer:
  • Print Preview support.
  • Line numbers available in Report Viewer through right-click context menu > Line Numbers.
  • Index available for text-based Static Timing Report.
• ISE Text Editor:
  • Wildcards supported in Find options
• RTL/Technology Viewer:
  • Several bugs fixed relating to the drawing of schematics, particularly when drawing buses.
  • Improvements to cross probing from Timing Analyzer to RTL/Technology Viewer.
• Schematic Editor:
  • Symbol preview diagram in Symbol Wizard.
  • Symbol attributes properly displayed on schematic sheet.
  • Several bugs fixed relating to the drawing and netlisting of schematics.
  • Mentor Graphics QuestaSim™ integrated simulation support.

Partial Reconfiguration

• What's New for Partial Reconfiguration in ISE 12.2:
  • Implementation tool runtimes improved more than 20%.
  • Improved DRCs.
  • Support for Virtex-6 LX/CXT low power (TL) and Qual (QX) devices.
  • Support for Virtex-6 HXT devices available upon request.
  • Encrypted partial bit files are supported for Virtex-6.
    

FPGA Editor

• List Window:
  • Double-click or use the pop-up menu to zoom to selected items.
• Array Window:
  • Right click to access the Hilite commands.
  • Use the Select Area command to select sites and comps within a rectangular region.
• Dialog Boxes:
  • New Automatic DRC on Save setting in Main Properties.
    

PlanAhead

• Design Preservation and Partial Reconfiguration are supported for the command line tools and the standalone version of the PlanAhead™ software.
• Spartan-6 SSO/SSN is supported using limit tables for calculating simultaneous I/O switching output/noise.

SmartXplorer

• SmartXplorer automatically runs BITGEN for the best strategy (command line mode only).
• SmartXplorer is capable of saving only the N best results in order to efficiently manage disk space.
• Project Navigator automatically passes user-set TRCE options to SmartXplorer.
• A new check button in Project Navigator activates Power Analyzer in SmartXplorer.
• Project Navigator allows you to personalize the SmartXplorer Run Summary table.
• Area data (LUTs, Slice registers) is visible in the SmartXplorer Run Summary table.

XST

• Allows you to use the timing command to generate clock domain crossing information.
  

What's New in the ISE Design Suite 12.1 for Logic Designers

Logic Edition Highlights

• Unlocking greater productivity, achieving breakthrough power and cost reductions, while optimizing performance with industry’s only domain-specific FPGA design suite.
• Achieving dramatic power reduction using Industry’s only automated clock-gating technology.
• Enabling lower system cost by delivering intuitive 4th generation partial reconfiguration design flow.

Reduced Runtime

• 2X faster runtimes for XST and 1.3X for implementation for large designs.
• Additional 15% - 20% faster implementation runtimes using multi-threading.

Usability Improvements

• XST support for BRAM inference with asymmetric ports.
• New PlanAhead User Interface.
• Project Navigator HDL parser analyzes sources to build hierarchy and create compile order list.
• ISim – EDK simulation support.
• Faster FPGA Editor response times.

Project Navigator

• Design Hierarchy Parsing Improvements:
  • Up-front HDL syntax error checking.
  • User control for enabling or disabling hierarchy reparsing.
  • Full support for `include files, including automatic detection of `include files, process dependency and source management.
  • Support for netlist sources (EDIF, NGC/NGO) as sub-modules in the design hierarchy, including process dependency and source management.
• "Find" Support in Design Hierarchy View:
  • Search for sources in the design hierarchy based on file name, module name, instance name, or for missing modules. 
• Process Status Improvements:
  • New Process Monitor.
  • Improved status indicator behavior.
  • Ability to run downstream processes based on presence of necessary files rather than error status of previous steps.
• Design Summary System Settings Report:
  • New System Settings report in Design Summary displays environment settings and process properties used during design implementation.

Power Optimization

Partial Reconfiguration

FPGA Editor

• Performance:
  • Approximately 40% smaller memory footprint for large devices compared to the 11.1 release.
  • Faster loading of device graphics.
  • Faster selection of multiple sites, components and wires.
• Main Window:
  • Title Bar displays full path to design.
  • History Toolbar displays design's creation date.
  • Status Bar displays Pattern Matching setting: Wild Cards or Reg Expr.
  • Menu command Tools > Run Bitgen provides quick access to the Bitgen program.
• List Window:
  • Copy, paste, cut keyboard shortcuts can be used in the Name Filter.
  • Delete or DEL key can be used to delete selected items.
• Array Window:
  • Tool tips are available for component pins and for all PIPs.
  • Layer Apply toolbar button is a time saver when toggling multiple layers on/off.
  • More than 100 additional highlight colors are available.
  • Zoom Selection toolbar button works correctly for pin wires.
• Block Window:
  • Select Component or Site dialog box now lists sites.
• Dialog Boxes:
  • Most dialog boxes are now resizable.
  • Net Goto Pins and Net Properties show the routed status of pins.
  • Main Properties has new setting: Automatically Load Delays.
  • Probes saves hilite colors in the probes.scr file.
  • ILA (ChipScope) now displays the Port #.

ChipScope

• Support added for Spartan-6Q devices.
• Support for continuous trigger with multiple ILA cores. A Repetitive Run Trigger option has been added to Analyzer - monitor repetitive events without having to manually re-arm the trigger.

Device Programming

• Support for JTAG cables sold by third-party partners ByteTools and Digilent has been added to iMPACT and ChipScope Pro.
• New Flash device support has been added to iMPACT.  The following third-party devices may be programmed:
  • Numonyx N25Q
  • Numonyx P30 (now up to 1Gb)
  • Winbond W25Q
  • Spansion S25FLP
  • Spansion S29GLP

ISim

• Improved integration and interoperability
  • Simulate embedded designs - Integration into XPS and Project Navigator.
• Complete OS Support
  • Native Windows-64 support.
• Ease of Use for batch-mode user
  • Programmatically configure waveform via Tcl.
• Memory viewing and debug
  • New Memory editor and viewers.
  • Automatically parses design and identifies memory elements.
• Waveform enhancements
  • Adjust timescale automatically for optimal viewing.
  • Override HDL stimulus with user-defined values.
• EDK Simulation support

PlanAhead

SmartXplorer

• Synthesis is now supported in SmartXplorer when using the command line. The new custom file format that was added to support this will also let you specify synthesis and implementation strategies simultaneously.
• In addition, you can do the following with new SmartXplorer options.
  • Display area information in the SmartXplorer report table by using the –area_report option.
  • Run power analyzer and display power information in the SmartXplorer report table by using the –pwo option (command line mode only).
  • Use power as an additional best strategy selection criterion, if you are using the –pwo option.
  • Control TRCE by using the –to option. This option lets you generate verbose TRCE reports during SmartXplorer runs.

XPower Analyzer

• Several views reorganized: related data is consolidated and has similar organization to XPE.
• By Hierarchy view:
  • Added resource utilization for each hierarchy level: LUTs, FFs
  • Additional statistic data in tool-tip window.
• By Clock Domain view:
  • Frequency for all clocks are now editable.
  • Added details regarding clock tree topology.
• Allows to specify custom Off-Chip I/O termination to calculate off-chip power.
  • By default tool no longer assumes any termination.
• Added Confidence Level view to assist user to obtain realistic power data.
• Text report changed: it is aligned with GUI report structure.

XPower Estimator

• Significantly improved readability
  • New color scheme
  • Improved presentation of data
  • Key results stand out
• Provides power distribution by resource type on Summary sheet.
• Reports total power supplied to I/O termination (off-chip power).
• Allows to specify custom Off-Chip I/O termination to calculate off-chip power.
  • By default tool no longer assumes any termination.
  • Topologies graphic included in XPE for user reference.
• Adds possibility to quickly estimate potential power savings when using ISE goals & strategies settings.

XST

• 2X synthesis runtime reduction for large designs.
• Inference support for asymmetric port block RAM.
• New intuitive and compact HDL coding templates to model block RAM with byte-write enable functionality.
• Power optimization dedicated to BRAM optimization is now implemented for Virtex-6 and Spartan-6. For more information see –power option and RAM Style (RAM_STYLE) constraint.
• A new automax value for the Use DSP Block (USE_DSP48) constraint. This value:
  • Instructs XST to maximize utilization of DSP resources within the limits of available resources on the selected device.
  • Allows you to implement more logic on DSP blocks than can typically be achieved with the auto value. This can be particularly useful when a tightly packed device is your primary concern.
• A new Shift Register Minimum Size (SHREG_MIN_SIZE) option allows you to control the minimum size of shift registers that are inferred and implemented using SRL-type resources. While the default minimal size is 2, you may need to raise that threshold for more efficient resource placement and circuit performance.
• Improved design methodology: specifying properties of instantiated device primitives can no longer be done by means of VHDL attributes, Verilog attributes, or XST Constraint File (XCF) constraints, and is now rejected. This must now be done with VHDL generics or Verilog parameters.