What's New in the ISE Design Suite 11.3 for Logic Designers

The ISE® Design Suite: Logic Edition delivers a complete design solution for designers focused on logic and connectivity. the ISE Design Suite: Logic Edition provides a complete flow that includes design creation, verification and implementation and includes improvements to address design pressures for faster time to production and optimal quality of results. The ISE Design Suite: Logic Edition includes the following products:

• ISE™ Foundation™ with the ISE™ Simulator
• PlanAhead™ Design and Analysis Tool
• ChipScope™ Pro and the ChipScope™ Pro Serial I/O Toolkit
• Foundation IP

The ISE Design Suite Logic Edition supports the base methodology and IP required for the Base Targeted Design Platform.

Download a free 30 day evaluation of the ISE Design Suite: Logic Edition and start your design today!

Support for the Virtex-6 HXT FPGA Platform

This latest release of the ISE Design Suite provides support for the new Virtex-6 HXT FPGA platform delivering the industry's highest bandwidth FPGA with up to 72 serial transceivers for high-bandwidth applications such as bridging, switching, and aggregation, in wired telecommunications and data communications systems.

Additional Improvements in the ISE Design Suite: Logic Edition 11.3

ChipScope Pro Enhancements

• The Integrated Bit Error Ratio Tester (IBERT) 2.0 now provides support for the Spartan-6 LXT FPGA Family

iMPACT Enhancements

• Reading and programming of eFUSE registers is now supported for devices in the Spartan-6 Family
• eFUSE support has been extended to support the Linux operating system in addition to the 32-bit version of Microsoft Windows

ISE Simulator (ISim) Enhancements

• File names in the ISim console now link to the associated file
• ISim users now have the ability to clear the console for greater ease-of-use

PlanAhead Design Analysis Tool Enhancements

• PlanAhead now supports the creation of DCI Cascade groups and membership editing
• A new SSN Predictor is now available when targeting Virtex-6 FPGAs
• New PlanAhead interface enhancements allow users to label pin rows in the package view when zooming
• Additional DRCs are available for designs targeting Virtex-6 and Spartan-6 FPGAs

Xilinx Power Analyzer (XPA) Enhancements

• The Xilinx Power Analyzer provides greater ease-of-use with:
  • New capabilities to interrupt the power analysis process
  • Support for bus reconstruction in the I/O view
  • The ability to select and edit multiple cells within the interface

New IP Cores in the ISE Design Suite 11.2

FPGA Features and Design

• Spartan-6 SelectIO Wizard v1.1 - Generates an HDL file that contains IO logic such as IOSERDES and IODELAY blocks customized to the user's interface requirements.
• Virtex-6 FPGA GTH Transceiver Wizard v1.1 - Generates a custom wrapper that configures one or more Virtex-6 FPGA GTH transceivers according to user requirements. In addition, it produces an example design, testbench, and scripts to allow you to observe the transceivers operating under simulation and in hardware.

Video and Image Processing

• Video On Screen Display v1.0 - A sophisticated module that provides three hardware accelerated functions including multiple alpha blending layer compositor, simplified graphics processing unit (boxes), and simplified text processing unit for video systems.
• Video Direct Memory Access v1.0 - Allows Video Cores to access external memory via the Video Frame Buffer Controller (VFBC) within the Multiport Memory Controller under control of the host processor.

Communication and Networking 

• RXAUI v1.1 - The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE IP provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2005. The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2005 clause 45 management registers.

Improvements in the Core Generator

• The Core Generator now checks for IP license availability before proceeding through the process of core generation.
• Automated core upgrade to latest version capability has been added for the following IP cores:
  • CIC Compiler v1.3
  • DDS Compiler v4.0
  • Distributed Memory v4.2
  • Multipler Generator v11.2

IP Core Updates

• Support for Virtex-6 HXT, Virtex-6 Lower Power, and Virtex-5Q have been added to selected cores in this release.
• A comprehensive listing of cores in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_3_datasheets.htm.
• For more information see www.xilinx.com/ipcenter/coregen/updates_11_3.htm

What's New in the ISE Design Suite 11.2 for Logic Designers

Introducing Virtex-6 and Spartan-6 Device Support

Experience a complete software flow for the new Virtex®-6 and Spartan®-6 targeted design platforms.  The ISE Design Suite includes new features specifically added to enhance Virtex-6 and Spartan-6 performance, as described below:

New VHDL/Verilog Parser for XST for Virtex-6 and Spartan-6

• Support for complex data structures
• Fixes long standing complexity problems, such as long runtime and memory usage
• Greater flexibility in design coding
• Easier migration of designs to Xilinx architectures
• Faster runtime for Virtex-6 and Spartan-6 FPGAs compared to preceding families

Timing Analyzer

• Multi-Corner Timing Analysis leveraged for improved timing analysis For Virtex-6
• Timing Analysis support for Virtex-6 and Spartan-6 ICAP component
• Asynchronous path tracing enabled for Virtex-6 and Spartan-6 FPGAs
  • Setup/hold (recovery/removal) checking on asynchronous pin of registers enabled by default
• Configuration simulation model enhancements
  • Support for ICAP for Spartan-6 and Virtex-6 FPGAs
  • Serial configuration supported in SIM_CONFIG models
  • SelectMAP configuration support for Virtex-6 and Spartan-6 FPGAs

Power Optimization and Analysis

• Easier comparison between device families in XPE
  • Combined XPE spreadsheets for Spartan-3A and Spartan-6 FPGAs
  • Combined XPE spreadsheets for Virtex-5 and Virtex-6 FPGAs

iMPACT

• eFUSE reading and programming is supported for Virtex-6 devices

ChipScope Pro

• Integrated Bit Error Ratio Tester (IBERT) 2.0 for Virtex-6 FPGAs
  • Graphical visualization of parameter sweep results
  • Similar look and feel as Rocket IO Wizard
  • Improved system clocking, including higher frequencies and ability to use REFCLK as system clock

Additional New Features in the ISE Design Suite: Logic Edition

Multi-Threading Supported Added for Plance and Route on Microsoft Windows

To enable users to achieve more turns per day and better explore multiple implementation options for best QoR, the ISE Design Suite provides support for multi-threaded place and route on both Linux and Microsoft Windows platforms.

Usability Improvements

• Project Navigator
  • Improvements to Project Navigator "Find-in-Files" capability for faster and more complete searching
  • Improvements to RTL/Technology schematic viewers to speed viewing of top-level design
  • Improvements to Constraints Editor to support direct "spreadsheet-style" constraint entry
• ISim GUI improvements
  • History of previous searches saved
  • –sourcelibdir switch added to ISim compiler (fuse) to emulate Cadence Verilog-XL “-y” behavior

New IP Cores in the ISE Design Suite 11.2

Bus Interface and IO

• Spartan-6 Integrated Block for PCI Express v1.1 - The Xilinx Spartan-6 Integrated Block for PCI Express uses the Spartan-6 Integrated Hard IP Block for PCI Express in conjunction with flexible Spartan-6 architectural features to implement a compliant PCI Express Endpoint
• Virtex-6 Integrated Block for PCI Express v1.2 - The Xilinx Virtex-6 Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) uses the Virtex-6 Integrated Hard IP Block for PCI Express in conjunction with flexible Virtex-6 architectural features to implement a PCI Express Base Specification v2.0 compliant PCI Express Endpoint. Unique features of the LogiCORE Block for PCI Express are the high performance LocalLink User Interface, optimal buffering for high bandwidth applications, and BAR checking and filtering.

Communication and networking

• Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper v1.2 – automates generation of HDL wrapper files with the correct attributes and physical interfaces for the user-selected configuration of the Virtex-6 Embedded Tri-Mode Ethernet MAC.

FPGA features and design 

• Spartan-6 FPGA RocketIO GTP Transceiver Wizard - automates generation of HDL wrapper files with the correct attributes and physical interfaces for Spartan-6 FPGA GTPA1 transceivers. 
• Virtex-6 FPGA RocketIO GTX Transceiver Wizard - automates generation of HDL wrapper files with the correct attributes and physical interfaces for Virtex-6 FPGA GTX transceivers.

IP Core Updates for Virtex-6 and Spartan-6

• A comprehensive listing of cores that have been updated with support for Virtex-6 and Spartan-6 in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_2_datasheets.htm.
• For more information see www.xilinx.com/ipcenter/coregen/updates.htm.

What's New in the ISE Design Suite 11.1 for Logic Designers

Ultimate Productivity

Licensing for the ISE Design Suite Managed by FLEXnet Publisher

All ISE Design Suite products and select Xilinx IP are now licensed using FLEXnet Publisher from Acresso Software Inc. The incorporation of this EDA industry standard licensing solution allows greater flexibility for ISE Design Suite Users.

Products can now be licensed in different ways to best suit a users needs:

• Floating and Triple-Redundant license servers now supported. One license shared by multiple users provides a cost-effective solution where multiple users can leverage a single seat.
• Node-lock licenses may use Host ID's from an Ethernet MAC address, hard-drive serial number, or dongle-based FLEXid's. In previous releases, IP node-lock licenses supported only Ethernet MAC addresses.
• Users are now able to better track usage to ensure compliance with the End User License Agreement using an industry standard licensing method.

Xilinx has simplified the process of obtaining and licensing software, allowing you to download and license Xilinx software and most other FLEXnet licensed Xilinx IP products from a single website. Customer license or CAD-tool administrators now have improved ability to manage Xilinx software and IP licenses from a single web-location IP licensing procedures now merged with software licensing flow.  This will greatly reduce the time it takes to obtain an IP license to just a few hours, or even minutes, in some cases.

Faster Runtimes for More "Turns-per-Day"

The ISE Design Suite 11 release offers improved runtimes over the previous major release at each step in the design flow including HDL synthesis, Place and Route, and verification. These improvements offer more design itterations, or "turns" per day delivering faster time to production.

• XST, the ISE Design Suite synthesis solution, delivers and average of 2X faster synthesis results
• The ISE Simulator provides up to 2X faster simulation times
• Improvements in the ISE place & route algorithms deliver an average 2X faster implementation times
• For faster incremental implementations, users can take advantage of the next generation of SmartGuide providing an average of 2X faster additional improvement. SmartGuide minimizes implementation differences between two versions of the same design resulting in, not only faster implementatin times, but reduced risk late in the project timeline.
• Xilinx leverages the latest encryption methodology as specified in Verilog LRM - IEEE Std 1364-2005. Virtex FPGA family simulation models for the Hard-IP such as PowerPC, MGT, and PCIe leverage this technology delivering over 2X faster times for PowerPC, MGT, and PCIe simulation. SecureIP models are supported by the following Xilinx and third-party partners:
  • ISE Simulator 11.1
  • Mentor ModelSIM 6.4b and above
  • Cadence NCSim 8.1 S009 and above
  • Synopsys VCS-MX 2008.09 and above

Support for Multi-Processor Implementation

To enable users to achieve more turns per day and better explore multiple implementation options for best QoR, the ISE Design Suite provides support for multi-threaded place and route. In addition, SmartXplorer delivers support for compute farm systems (Load Sharing Facility & Sun Grid Engine).

Next Generation SmartGuide

With SmartGuide, users are able to limit re-implementation to only the affected areas for small design changes outside of critical path. This greatly reduces the time required for incremental implementation for faster time to production. In addition, preserving results from previously successful implementations reduces surprises late in the project timeline.

One-Click Insertion of ChipScope Pro Cores Using PlanAhead

With the ISE Design Suite 11, users can now easily insert ChipScope Pro cores using the rich graphical interface of the PlanAhead design and analysis tool. This streamlined access to powerful on-chip verification allows usres to focus on their methodology and not the tools.

Improved Memory Utilization

Optimizations in synthesis and implementation deliver an average of 28% better memory utilization. These improvements allow more efficient compilation of very large designs on mid-range platforms with a 32-bit operating systems.

Optimal Performance

All Editions of the ISE Design Suite Now Include the PlanAhead Design and Analysis Tool

PlanAhead provides an environment to help users achieve even greater design results. PlanAhead allows users to divide a larger design into smaller, more manageable blocks and focus efforts toward optimization of each module.

ExploreAhead technology in PlanAhead is an implementation exploration tool. By managing multiple implementation runs, ExploreAhead allows the user to execute multiple implementation runs based on strategies they’ve defined or predefined strategies shipped as factory defaults.

XST Synthesis Improvements

The ISE Design Suite delivers better results though improvements in the Xilinx Synthesis Solution (XST). These improvements include:

• Better handling of BRAMs in byte-write enable mode
• Improved processing of dual-port BROMs
• Better register absorption for DSP blocks

Improved Power Optimization

Through easily accessible options in implementation, the ISE Design Suite delivers an easy and convenient method to reduce dynamic power by an average of 10%. Improvements in the ISE Design Suite 11 enable logic re-synthesis to reduce the number of switching elements and clock gating in the Placer. Algorithms in the Placer use a global clock buffer to replace high fanout register clock enables.

Vectorless Power Estimation and Improved Power Estimation Accuracy

With power being a high priority obstical for designers, improved power estimation early in the design process reduces surprise and frustration later in the design.Improvements in the power estimation algorithms simplifies the process of developing and early and accurate power budget.