Xilinx Platform Studio (XPS)

The Zynq™ 7000 SoC delivers the pinacle of SoCs functionality through dual ARM Cortex A9 dual microprocessors, and a hardened peripheral set with functions such as Ethernet, I2C, SDIO, USB, and CAN; coupled with AMD programmable logic where custom soft peripherals and logic, devices and accelerators can be instantiated. XPS accelerates every aspect of design creation for Zynq devices through easy-to-use graphical wizards including clock domain setup, interupts, DMAs, external connections for the hardened peripherals, and interface connections for the soft peripherals in programmable logic. This means that designers can immediately begin their custom design without fear of defining incompatible interfaces or connections.

• AXI Interfaces
  • General-Purpose 32-bit AXI Master/Slave Ports
  • High-Speed 32/64-bit AXI Slave Ports
  • 64-bit AXI Accelerator Coherency Port
  • General purpose DMA controllers
• Systems, peripherals, trace and debug clocks
• Hardened Zynq-EPP peripheral interfaces
  • Quad SPI/SRAM/NOR/NAND Flash
  • Gigabit Ethernet
  • USB 2.0
  • Secure Digital
  • UART
  • I2C
  • SPI
  • CAN
  • GPIO
• Interrupts
• Peripheral connections to Multiplexed I/O

With extraordinary scalability and customization potential, ranging from an 8-bit state machine all the way up to complex, SoC-like 32 bit RISC designs, Microblaze™ meets a diverse set of project-specific processing requirements. Engineers can create hundreds of different Microblaze designs by using XPS to integrate pre-validated processor-internal IP such as pipelines, clocks, timers, and interrupt controllers; and processor-peripheral IP; such as memory controllers, USB, CAN bus, I2C, Ethernet, FPU, and much more that are available through the AMD Embedded IP catalog. When this off-the-shelf processor configuration capability is combined with the ability to integrate 3rd party RTL and custom-IP blocks, engineers can truly produce unique, custom designs that meet their precise requirements.

XPS supports drag-and-drop integration of IP cores from the AMD Embedded IP catalog, within custom processor designs. Examples of such IP cores include peripherals, devices and accelerators such as AXI bridges, GPIO, PLBV4.6 bridge, BRAM and external memory controllers, Serial Peripheral and QuadSPI Interfaces, Analog to Digital converters, Graphics, Clocks and Timers, UARTs, I2C, Interrupt controllers and much more.

Although many kinds of systems can be created from the peripherals available within the AMD catalog, it is often necessary to create and import custom peripherals for new functionality. The AMD Create and Import Peripheral wizard allows hardware designers to create AXI (version 4) peripherals in Verilog or VHDL, or both (for a mixed-language design) and then to import them into an XPS projects for connection to any AXI4-Lite, AXI4 (Burst-enabled) and AXI4-Stream interface. This wizard also enables you to integrate your PLB (version 4.6) or FSL peripherals PLB-based designs. Upon import into XPS, your custom peripheral is managed just like any off-the-shelf module available from the AMD Embedded IP catalog.

XPS makes it easy to connect each of the IO pins, or internal programmable logic end-points to their desired end-point. XPS easily manages this for connections that link off-chip to the PC board via a physical pin, or to another device within the programmable logic, XPS guarantees proper routing, signal and voltage-rail correctness.For the Zynq 7000 SoC device family, XPS also manages configuration of the built in IO multiplexer which routes the processing system devices to their appropriate output pins.

Custom designs that are built around programmable logic such as AMD FPGAs or Zynq 7000 SoC require custom firmware that manages the custom hardware all the way from first stage boot, through to device instantiation (bit stream), initialization, and finally to device-specific interface (by the software stack). The creation of such firmware can be very challenging due to the strict dependencies between the firmware development and the custom hardware design. XPS avoids this problem by sharing hardware, project and design-specific information with SDK which is then able to automatically configure, build and deploy critical, design-specific firmware including:

• First stage boot loaders
• Security software (boot loader, firmware)
• Bitstream Management

For Devices that have been drawn from the AMD Embedded IP catalog, SDK also auto-generates bare-metal drivers and BSP – for inclusion within OS-less code or RTOS, and also Linux drivers and BSP. In this manner, XPS allows designers to largely ignore firmware and low-level BSP development that are otherwise required prior to proceeding with boot, OS and application development.