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Advanced Features and Techniques of Embedded System Software Design

Release Date:
November 2017
Level:
Embedded Software 4
Duration:
1 day

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Key Documentation

Audience

Software design engineers interested in fully utilizing the Zynq® extensible processing platform.

Prerequisites

  • Embedded Systems Software Design or equivalent knowledge
  • C or C++ programming experience
  • Conceptual understanding of embedded processing systems, including device drivers, interrupt routines, Xilinx Standalone library services, user applications, and boot loader operation
  • Experience developing software for embedded processor applications

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course will help software engineers make full use of the components available in the Zynq® All Programmable System on a Chip (SoC) processing system (PS). This course covers advanced Zynq All Programmable SoC topics for the software engineer, including advanced boot methodology, the NEON co-processor, programming PS system-level function control registers, the general interrupt controller, the DMA, Ethernet, and USB controllers, and the various low-speed peripherals included in the Zynq All Programmable SoC processing system. 

Software Tools

Vivado® Design or System Edition 2017.3

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

*This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Implement an effective Zynq All Programmable SoC boot design methodology
  • Create an appropriate FSBL image for flash
  • Identify advanced Cortex™-A9 processor services for fully utilizing the capabilities of the Zynq All Programmable SoC
  • Analyze the operation and capabilities of the DMA controller in the Zynq All Programmable SoC
  • Examine the various Standalone library services and performance capabilities of the Ethernet and USB controllers in the Zynq All Programmable SoC
  • Describe the Standalone library services available for low-speed peripherals that are contained in the Zynq All Programmable SoC PS

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Booting: Overview Introduces the main points to how booting a processor is handled in Zynq All Programmable devices and MicroBlaze processors.
  2. 1.2
    Booting: Boot Memory Technologies Introduces the main points of the memories that can be booted or executed from.
  3. 1.3
    Booting: Flow Provides a low-level view of the booting process.
  4. 1.4
    Booting: PS Processors Introduces the concepts behind a single-core boot, a dual-core boot, and symmetric or asymmetric processing.
  5. 1.5
    Booting: PL Introduces the concepts behind configuring the PL at boot.
  6. 1.6
    Booting: Secure Boot Introduces the concepts behind secure booting.
  7. 1.7
    Booting: FSBL Introduces the First Stage Boot Loader (FSBL).
  8. 1.8
    General Interrupt Controller Introduces the general interrupt controller (GIC), its features, and some examples of its use.
  9. 1.9
    Processor Caching and SCLR Introduces the concepts behind processing caching and the System-Level Control Register.
  10. 1.10
    NEON Co-Processing Introduces the concepts behind the NEON co-processor.
  11. 1.11
    DMA: Introduction and Features Introduces the direct memory access controller.
  12. 1.12
    DMA: Block Design and Interrupts Introduces the DMA block design and the DMA interrupts.
  13. 1.13
    DMA: Read and Write Introduces the concepts behind DMA reading and writing.
  14. 1.14
    High-Speed Peripherals: Gigabit Ethernet Introduces the Gigabit Ethernet high-speed peripheral.
  15. 1.15
    High-Speed Peripherals: USB Introduces the USB high-speed peripheral.
  16. 1.16
    Low-Speed Peripherals: Overview Introduces the low-speed peripherals in the Zynq All Programmable SoC.
  17. 1.17
    Low-Speed Peripherals: UART Introduces the UART low-speed peripheral.
  18. 1.18
    Low-Speed Peripherals: CAN Introduces the CAN low-speed peripheral.
  19. 1.19
    Low-Speed Peripherals: I2C Introduces the I2C low-speed peripheral.
  20. 1.20
    Low-Speed Peripherals: SPI Introduces the SPI low-speed peripheral.
  21. 1.21
    Low-Speed Peripherals: SD/SDIO Introduces the SD/SDIO low-speed peripheral.
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