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Advanced VHDL

Release Date:
May 2017
Level:
FPGA 4
Duration:
2 days

Key Documentation

Audience

VHDL users with intermediate knowledge of VHDL

Prerequisites

  • Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
  • At least 6 months of coding experience beyond an introductory course

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.

The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.

Software Tools

  • Vivado® Design or System Edition 2017.1

Hardware

  • Architecture: N/A*
  • Demo board: None*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Write efficient and reusable RTL, testbenches, and packages
  • Create self-testing testbenches
  • Create realistic models
  • Use the text IO capabilities of the VHDL language
  • Store simulation data dynamically
  • Create parameterized designs
  • Create parameterized code for design reuse

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    VHDL Overview
  2. 1.2
    Simulation Concepts
  3. 1.3
    Advanced Data Types
  4. 1.4
    Subprograms and Design Attributes
  5. 1.5
    Lab 1: Flexible Functions Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
  6. 1.6
    Access Type Techniques and Blocks
  7. 1.7
    Lab 2: Linked Lists with Access Types Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
  8. 1.8
    Utilizing File IO
  9. 1.9
    Lab 3: TextIO Techniques Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.

Day 2

  1. 2.1
    Advanced Techniques in VHDL
  2. 2.2
    Lab 4: Creating Real-World Simulations Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
  3. 2.3
    Supporting Multiple Platforms
  4. 2.4
    Lab 5: Supporting Multiple Platforms Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
  5. 2.5
    Non-Integer Numbers
  6. 2.6
    Lab 6: Implementing Fixed and Floating Point Numbers Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.
  7. 2.7
    Appendix: Guarded Signals
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