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C-based HLS Coding for Hardware Designers

Release Date:
October 2012
Level:
DSP 3
Duration:
1 day

Quick Links

Key Documentation

Audience

Hardware engineers looking to utilize high-level synthesis

Prerequisites

  • C, C++, or System C knowledge
  • HDL knowledge
  • Hardware design

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides hardware engineers with sufficient knowledge of C-programming techniques for Vivado® HLS to take advantage of Xilinx FPGAs. Learn high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.

Software Tools

  • Vivado System Edition 2012.2

Hardware

  • Architecture: Zynq®-7000 All Programmable SoC and 7 series FPGAs*
  • Demo board: None

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the difference between software programming and hardware design
  • Model and simulate hardware components using C
  • Code hardware components in C for high-level synthesis

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to Software Design for Hardware Designers
  2. 1.2
    C-based Algorithmic Coding for Hardware
  3. 1.3
    Lab 1: High-Level Synthesis of a C Model Use various techniques and directives in Vivado HLS to improve design performance. The design under consideration accepts an image in a (custom) RGB format, converts it to the Y’UV color space, and applies a filter to the Y’UV image and converts it back to RGB.
  4. 1.4
    C-based Test Bench Coding
  5. 1.5
    Lab 2: Creating a C-based Test Bench Develop a verification environment used for testing a C-based design and verification in Vivado HLS. The design under consideration is the same design used in the previous lab, a Y’UV filter.
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