FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado® Design Suite
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer.
* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will have the necessary skills to: