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Designing an Integrated PCI Express System

Release Date:
June 2017
Level:
Connectivity 3
Duration:
2 days

Key Documentation

Audience

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express® specification
  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Prerequisites

  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Software Tools

  • Vivado Design or System Edition 2017.1

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*

* This course focuses on the 7 series architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Construct a basic PCIe system by:
    • Selecting the appropriate core for your application
    • Specifying requirements of an endpoint application
    • Connecting this endpoint with the core
    • Utilizing FPGA resources to support the core
    • Simulating the design
  • Identify the advanced capabilities of the PCIe specification protocol and feature set

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Course Introduction
  2. 1.2
    Lab 0: Packaet Coding This lab helps you recall basic PCI Express transaction layer packet formats.
  3. 1.3
    Xilinx PCI Express Solutions
  4. 1.4
    Connecting Logic to the Core – AXI Interface
  5. 1.5
    PCIe Core Customization
  6. 1.6
    Lab 1: Constructing the PCIe Core This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
  7. 1.7
    Packet Formatting Details
  8. 1.8
    Simulating a PCIe System Design
  9. 1.9
    Lab 2: Simulating the PCIe Core This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
  10. 1.10
    Endpoint Application Considerations
  11. 1.11
    PCI Express in Embedded Systems

Day 2

  1. 2.1
    Lab 3: Using the PCI Express Core in IP Integrator This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
  2. 2.2
    Application Focus: DMA
  3. 2.3
    Design Implementation and PCIe Configuration
  4. 2.4
    Lab 4: Implementing the PCIe Design This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
  5. 2.5
    Root Port Applications
  6. 2.6
    Debugging and Compliance
  7. 2.7
    Lab 5: Debugging the PCIe Design This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.
  8. 2.8
    Interrupts and Error Management
  9. 2.9
    Course Summary
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