We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Designing with SystemVerilog

Release Date:
June 2018
2 days

Quick Links

Key Documentation


FPGA designers and logic designers



For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

Software Tools

  • Vivado® Design or System Edition 2018.1
  • Questa Sim Prime Simulator 10.6c


  • Architecture: N/A*
  • Demo board: Kintex® UltraScale™ FPGA KCU105 board or Kintex-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for RTL design
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to use structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize Xilinx FPGAs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to SystemVerilog Provides an introduction to the SystemVerilog language.
  2. 1.2
    Data Types Describes the data types supported by SystemVerilog.
  3. 1.3
    User-Defined and Enumerated Data Types Describes user-defined and enumerated data types supported by SystemVerilog.
  4. 1.4
    Type Casting Describes type casting in SystemVerilog.
  5. 1.5
    Arrays and Strings Explains the use of arrays in SystemVerilog.
  6. 1.6
    SystemVerilog Building Blocks Describes the design and verification building blocks in SystemVerilog.
  7. 1.7
    Structures Explains the use of structures in SystemVerilog.
  8. 1.8
    Unions Explains the use of unions in SystemVerilog.
  9. 1.9
    Additional Operators in SystemVerilog Describes the operators supported by SystemVerilog beyond those found in Verilog.

Day 2

  1. 2.1
    Procedural Statements Describes the different procedural blocks provided by SystemVerilog.
  2. 2.2
    Control Flow Statements Describes the different control statements provided by SystemVerilog.
  3. 2.3
    Functions Explains the SystemVerilog enhancements to functions.
  4. 2.4
    Tasks Describes the task SystemVerilog construct.
  5. 2.5
    Packages Describes the package SystemVerilog construct.
  6. 2.6
    Interfaces Describes the concept of interfaces in SystemVerilog.
  7. 2.7
    Targeting Xilinx FPGAs Focuses on Xilinx-specific implementation and chip-level optimization.
Page Bookmarked