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Designing with Verilog

Release Date:
May 2017
3 days

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Key Documentation


Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs


  • Basic digital design knowledge


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Software Tools

  • Vivado® Design or System Edition 2018.1


  • Architecture: N/A*
  • Demo board: Kintex® UltraScale™ FPGA KCU105 or Kintex-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the Vivado Design Suite environment
  • Download to the evaluation demo board 

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to Verilog
  2. 1.2
    Verilog Keywords and Identifiers
  3. 1.3
    Verilog Data Values and Number Representation
  4. 1.4
    Verilog Data Types
  5. 1.5
    Verilog Buses and Arrays
  6. 1.6
    Verilog Modules and Ports
  7. 1.7
    Verilog Operators
  8. 1.8
    Continuous Assignment
  9. 1.9
    Gate-Level Modeling
  10. 1.10
    Procedural Assignment
  11. 1.11
    Blocking and Non-Blocking Procedural Assignment
  12. 1.12
    Procedural Timing Control

Day 2

  1. 2.1
    Verilog Conditional Statements: if_else
  2. 2.2
    Verilog Conditional Statements: case
  3. 2.3
    Verilog Loop Statements
  4. 2.4
    Introduction to Verilog Testbenches
  5. 2.5
    System Tasks
  6. 2.6
    Verilog Sub-Programs
  7. 2.7
    Verilog Functions
  8. 2.8
    Verilog Tasks
  9. 2.9
    Verilog Compiler Directives
  10. 2.10
    Verilog Parameters
  11. 2.11
    Verilog Generate Statement

Day 3

  1. 3.1
    Verilog Timing Checks
  2. 3.2
    Finite State Machines
  3. 3.3
    Mealy Finite State Machine
  4. 3.4
    Moore Finite State Machine
  5. 3.5
    FSM Coding Guidelines
  6. 3.6
    Avoiding Race Conditions
  7. 3.7
    File I/O: Introduction
  8. 3.8
    File I/O: Read Functions
  9. 3.9
    File I/O: Write Functions
  10. 3.10
    Targeting Xilinx FPGAs
  11. 3.11
    User-Defined Primitives
  12. 3.12
    Programming Language Interface
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