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Designing with VHDL

Release Date:
June 2018
Level:
FPGA 1
Duration:
3 days

Key Documentation

Audience

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

Prerequisites

  • Basic digital design knowledge

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

In this three-day course, you will gain valuable hands-on experience.

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. 

Software Tools

  • Vivado® Design or System Editon 2018.1

Hardware

  • Architecture: N/A*
  • Demo board: Kintex® UltraScale™ FPGA KCU105 or Kintex-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will know how to:

  • Implement the VHDL portion of coding for synthesis
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
    • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the Vivado Design Suite environment             

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to VHDL Discusses the history of the VHDL language and provides an overview of the different features of VHDL.
  2. 1.2
    VHDL Design Units Provides an overview of typical VHDL code.
  3. 1.3
    VHDL Objects, Keywords, Identifiers Discusses the data objects that are available in the VHDL language as well as keywords and identifiers.
  4. 1.4
    Scalar Data Types Covers both intrinsic and commonly used data types.
  5. 1.5
    Composite Data Types Covers composite data types (arrays and records).
  6. 1.6
    VHDL Operators Reviews all VHDL operator types.
  7. 1.7
    Concurrency in VHDL Describes concurrent statements and how signals help in achieving concurrency.
  8. 1.8
    Concurrent Assignments Covers both conditional and unconditional assignments.
  9. 1.9
    Processes and Variables Introduces sequential programming techniques for a concurrent language. Variables are also discussed.

Day 2

  1. 2.1
    Conditional Statements in VHDL: if/else, case Describes conditional statements such as if/else and case statements.
  2. 2.2
    Sequential Looping Statements Introduces the concept of looping in both the simulation and synthesis environments.
  3. 2.3
    Delays in VHDL: Wait Statements Covers the wait statement and how it controls the execution of the process statement.
  4. 2.4
    Introduction to the VHDL Testbench Introduces the concept of the VHDL testbench.
  5. 2.5
    VHDL Assert Statements Describes the concept of VHDL assertions.
  6. 2.6
    VHDL Attributes Describes attributes, both predefined and user defined.
  7. 2.7
    VHDL Subprograms Covers the use of subprograms in verification and RTL code to model functional blocks.
  8. 2.8
    VHDL Functions Describes functions, which are integral to reusable and maintainable code.
  9. 2.9
    VHDL Procedures Describes procedures, common constructs that are also important for reusing and maintaining code.

Day 3

  1. 3.1
    VHDL Libraries and Packages Demonstrates how libraries and packages are declared and used.
  2. 3.2
    Interacting with the Simulation Describes how to interact with a simulation via text I/O.
  3. 3.3
    Finite State Machine Overview Provides an overview of finite state machines, one of the more commonly used circuits.
  4. 3.4
    Mealy Finite State Machine Describes the Mealy FSM and how to code for it.
  5. 3.5
    Moore Finite State Machine Describes the Moore FSM and how to code for it.
  6. 3.6
    FSM Coding Guidelines Discusses FSM implementation in an FPGA using VHDL.
  7. 3.7
    Vivado Simulator and Race Conditions in VHDL Introduces the Vivado simulator simulation environment. Race conditions are also discussed.
  8. 3.8
    Writing a Good Testbench Explores how time-agnostic, self-checking testbenches can be written and applied.
  9. 3.9
    Targeting Xilinx FPGAs Focuses on Xilinx-specific implementation and chip-level optimization.
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