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Developing and Optimizing Applications Using the OpenCL Framework for FPGAs

Release Date:
November 2016
Level:
SDx 2
Duration:
2 days

Quick Links

Key Documentation

Audience

Software and hardware developers who want to develop OpenCL, C/C++, and RTL applications in the SDAccel development environment.

Prerequisites

  • Basic knowledge of C/C++

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel™ development environment for use on Xilinx FPGAs. Porting existing applications is also covered.

This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.

Software Tools

  • SDAccel development environment and common build tools

* This course focuses on the 7 series, UltraScale, and UltraScale+ architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Identify parallel computing applications suitable for accelerating on FPGAs
  • Discover how the FPGA architecture lends itself to parallel computing
  • Write OpenCL programs for FPGAs
  • Examine the OpenCL execution model
  • Analyze the OpenCL memory model
  • Profile and debug OpenCL code using the SDAccel development environment
  • Discover how to maximize performance in FPGA fabric
  • Efficiently utilize FPGA memory resources
  • Utilize the SDAccel development environment
  • Rapidly develop FPGA applications using OpenCL
  • Port programs written in OpenCL for CPUs or GPUs to Xilinx FPGAs

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to OpenCL
  2. 1.2
    Comparison of CPU, GPU, and FPGA Architectures
  3. 1.3
    OpenCL Support for Xilinx FPGAs
  4. 1.4
    FPGA Hardware Details
  5. 1.5
    Introduction to the OpenCL API
  6. 1.6
    Lab 1: Creating an OpenCL Program from Scratch Creating an OpenCL Program from Scratch – Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations.
  7. 1.7
    OpenCL Execution Model
  8. 1.8
    Lab 2: Vector Addition Vector Addition – Learn how to execute parallel kernels.
  9. 1.9
    Memory Hierarchy
  10. 1.10
    Profiling and Debugging
  11. 1.11
    Lab 3: Pi by Monte Carlo Processes Pi by Monte Carlo Processes – Implement the Pi by Monte Carlo processes.
  12. 1.12
    Optimization
  13. 1.13
    Lab 4: Maximizing Performance Maximizing Performance – Use vector data types and increase bandwidth.
  14. 1.14
    Lab 5: Optimizing Kernels Optimizing Kernels – Use Loop Unrolling and Loop Pipelining.

Day 2

  1. 2.1
    Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging
  2. 2.2
    Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI Profiling and Debugging Using the SDAccel Development Environment GUI – Learn how to use interactive programming tools to improve performance and squash bugs.
  3. 2.3
    Using Existing C/C++ Code as Kernels in OpenCL
  4. 2.4
    Lab 7: Optimizing C/C++ Code for OpenCL Optimizing C/C++ Code for OpenCL – Convert existing C/C++ code into a kernel that can be used by OpenCL
  5. 2.5
    RTL IP as Kernels in OpenCL
  6. 2.6
    Lab 8: Using an RTL Kernel Using an RTL Kernel – Learn how to use existing, highly optimized IP in a new OpenCL application.
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