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Embedded Systems Design

Release Date:
April 2018
Embedded Hardware 3
2 days

Key Documentation


Engineers who are interested in developing embedded systems with the Xilinx Zynq® SoC, Zynq UltraScale+™ MPSoC, and/or MicroBlaze™ soft processor core.


  • FPGA design experience
  • Completion of the Designing FPGAs Using the Vivado Design Suite 2 course or equivalent knowledge of Xilinx Vivado® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado Design Suite. The features and capabilities of both the Zynq System on a Chip (SoC), Zynq UltraScale+ MPSoC, and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.

The Xilinx Zynq families enable a new level of system design capabilities over previous embedded technologies, which is highlighted throughout the course.

Software Tools

  • Vivado Design or System Edition 2018.1


  • Architecture: Zynq-7000 SoC (Cortex™-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors) and MicroBlaze processor*
  • Demo board: Zynq-7000 SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 SoC and Zynq UltraScale+ MPSoC architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The Zynq UltraScale+ MPSoC software projects use QEMU rather than a physical board.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing a Cortex-A9/A53/R5 processor using the Vivado IP integrator and Customization Wizard
  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
  • Create and integrate an IP-based processing system component in the Vivado Design Suite
  • Design and add a custom AXI interface-based peripheral to the embedded processing system
  • Simulate a custom AXI interface-based peripheral using verification IP (VIP)

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Embedded UltraFast Design Methodology Outlines the different elements that comprise the Embedded Design Methodology.
  2. 1.2
    Overview of Embedded Hardware Development Overview of the embedded hardware development flow.
  3. 1.3
    Driving the IP Integrator Tool Describes how to access and effectively use the IPI tool.
  4. 1.4
    Overview of Embedded Software Development Reviews the process of building a user application.
  5. 1.5
    Driving the SDK Tool Introduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application.
  6. 1.6
    AXI: Introduction Introduces the AXI protocol.
  7. 1.7
    AXI: Variations Describes the differences and similarities among the three primary AXI variations.
  8. 1.8
    AXI: Transactions Describes different types of AXI transactions.
  9. 1.9
    Introduction to Interrupts Introduces the concept of interrupts, basic terminology, and generic implementation.
  10. 1.10
    Interrupts: Hardware Architecture and Support Reviews the hardware that is typically available to help implement and manage interrupts.

Day 2

  1. 2.1
    AXI: Connecting AXI IP Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
  2. 2.2
    Creating a New AXI IP with the Wizard Explains how to use the Create and Import Wizard to create and package an AXI IP.
  3. 2.3
    AXI: BFM Simulation Using Verification IP Describes how to perform BFM simulation using the Verification IP.
  4. 2.4
    MicroBlaze Processor Architecture Overview Overview of the MicroBlaze microprocessor architecture.
  5. 2.5
    MicroBlaze Processor Block Memory Usage Highlights how block RAM can be used with the MicroBlaze processor.
  6. 2.6
    Zynq-7000 SoC Architecture Overview Overview of the Zynq-7000 SoC architecture.
  7. 2.7
    Zynq UltraScale+ MPSoC Architecture Overview Overview of the Zynq UltraScale+ MPSoC architecture.
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