Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.
Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture.
This course covers ISE software features such as the CORE Generator® interface, I/O planning, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.
For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.
After completing this comprehensive training, you will have the necessary skills to: