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Introduction to the Zynq All Programmable SoC Architecture

Release Date:
November 2017
Level:
Embedded Hardware and Firmware 3
Duration:
1 day

Quick Links

Key Documentation

Audience

Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq® All Programmable SoC and programmable logic.

Prerequisites

  • FPGA design experience
  • Completion of the Designing FFPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado® Design Suite implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course provides hardware and firmware engineers with the knowledge to effectively utilize a Zynq All Programmable System on a Chip (SoC). It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL).

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the configuration options for the Zynq All Programmable SoC

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Overview Provides a general overview of the Zynq All Programmable SoC.
  2. 1.2
    Application Processor Unit (APU) Explores the individual components that comprise the APU.
  3. 1.3
    Processor Input/Output Peripherals Introduces the components that comprise the IOP block of the Zynq device PS.
  4. 1.4
    PS-PL Interface Describes in detail the PS interconnect and how it affects PL architecture decisions.
  5. 1.5
    Booting Explains the boot process of the PC and configuration of the PL.
  6. 1.6
    Memory Resources Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
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