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PCIe Protocol Overview

Release Date:
March 2011
Connectivity 2
1 day

Key Documentation


FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCI Express® protocol




For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course focuses on the fundamentals of the PCI Express protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.

Implementation issues are covered in the two-day Designing an Integrated PCI Express System course.

Software Tools

  • None required
  • VCD viewer optional


  • Architecture: N/A*
  • Demo board: None*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Interpret various transactions occurring on the link
  • Describe the layered architecture and the tasks and packet types each is responsible for
  • Properly estimate maximum performance of a link
  • Illustrate how errors can be communicated within the system
  • Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
  2. 1.2
    Introduction to the PCIe Architecture
  3. 1.3
    Review of the PCIe Protocol
  4. 1.4
    Packet Formatting Details
  5. 1.5
    Lab 1: Packet Decoding This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.
  6. 1.6
    Packet Routing
  7. 1.7
    Interrupts and Error Management
  8. 1.8
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