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UltraFast Design Methodology

Release Date:
December 2017
Level:
FPGA 3
Duration:
2 days

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Key Documentation

Audience

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Prerequisites

  • Some knowledge of FPGA design techniques is helpful
  • Experience with the Vivado® Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
  • Intermediate knowledge of Verilog or VHDL 

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Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs**
  • Demo board: None*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the UltraFast Design Methodology Checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    UltraFast Design Methodology: Introduction Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist.
  2. 1.2
    UltraFast Design Methodology: Board and Device Planning Introduces the methodology guidelines on board and device planning.
  3. 1.3
    Vivado Design Suite I/O Pin Planning Use the I/O Pin Planning layout to perform pin assignments in a design.
  4. 1.4
    Xilinx Power Estimator Spreadsheet Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
  5. 1.5
    Introduction to FPGA Configuration Describes how FPGAs can be configured.
  6. 1.6
    UltraFast Design Methodology: Design Creation Introduces the UltraFast methodology guidelines on design creation.
  7. 1.7
    HDL Coding Techniques Covers basic digital coding guidelines used in an FPGA design.
  8. 1.8
    Resets Investigates the impact of using asynchronous resets in a design.
  9. 1.9
    Register Duplication Use register duplication to reduce high fanout nets in a design.
  10. 1.10
    Pipelining Use pipelining to improve design performance.
  11. 1.11
    Synchronous Design Techniques Introduces synchronous design techniques used in an FPGA design.
  12. 1.12
    Creating and Packaging Custom IP Create your own IP and package and include it in the Vivado IP catalog.

Day 2

  1. 2.1
    Designing with the IP Integrator Use the Vivado IP integrator to create the uart_led subsystem.
  2. 2.2
    Revision Control Systems in the Vivado Design Suite Use version control systems with Vivado design flows.
  3. 2.3
    UltraFast Design Methodology: Implementation Introduces the methodology guidelines on implementation.
  4. 2.4
    Synthesis and Implementation Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
  5. 2.5
    Incremental Compile Flow Utilize the incremental compile flow when making last-minute RTL changes.
  6. 2.6
    UltraFast Design Methodology: Design Closure Introduces the UltraFast methodology guidelines on design closure.
  7. 2.7
    Introduction to Vivado Reports Generate and use Vivado reports to analyze failed paths.
  8. 2.8
    Baselining Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  9. 2.9
    Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing.
  10. 2.10
    Synchronization Circuits Use synchronization circuits for clock domain crossings.
  11. 2.11
    Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning.
  12. 2.12
    Congestion Identifies congestion and addresses congestion issues.
  13. 2.13
    Physical Optimization Use physical optimization techniques for timing closure.
  14. 2.14
    Power Management Techniques Identify techniques used for low power design.
  15. 2.15
    Vivado Design Suite Debug Methodology Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer.
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