Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.
This course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.
* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.
After completing this comprehensive training, you will have the necessary skills to: