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Vivado Design Suite for ISE Software Project Navigator Users

Release Date:
June 2018
2 days

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Key Documentation


Existing Xilinx ISE® software Project Navigator FPGA designers


  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

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For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course offers introductory training on the Vivado Design Suite. This course is for experienced ISE software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

Software Tools

  • Vivado System Edition 2018.1


  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the Project Manager in the Vivado Design Suite to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation) and analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Apply HDL coding techniques and reset methodology to your design
  • Utilize a systematic approach to apply synchronous design techniques
  • Use the Vivado IP flow to add and customize IPs
  • Explain how to use Tcl commands and scripts in your design 
  • Write Tcl scripts in Vivado Design Suite project and non-project modes

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to the Vivado Design Suite Introduces the Vivado Design Suite.
  2. 1.2
    Introduction to Vivado Design Flows Introduces the Vivado design flows: the project flow and non-project batch flow.
  3. 1.3
    Vivado Design Suite Project Mode Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
  4. 1.4
    Behavioral Simulation Performs behavioral simulation for your design.
  5. 1.5
    Synthesis and Implementation Create timing constraints according to the design scenario and synthesize and implement the design.
  6. 1.6
    Basic Design Analysis in the Vivado IDE Use the various design analysis features in the Vivado Design Suite.
  7. 1.7
    Vivado Design Suite I/O Pin Planning Use the I/O Pin Planning layout to perform pin assignments in a design.
  8. 1.8
    Xilinx Power Estimator Spreadsheet Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
  9. 1.9
    UltraFast Design Methodology: Board and Device Planning Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
  10. 1.10
    HDL Coding Techniques Covers basic digital coding guidelines used in an FPGA design.
  11. 1.11
    Resets Investigates the impact of using asynchronous resets in a design.
  12. 1.12
    Register Duplication Use register duplication to reduce high fanout nets in a design.
  13. 1.13
    Synchronous Design Techniques Introduces synchronous design techniques used in an FPGA design.

Day 2

  1. 2.1
    Vivado IP Flow Customize IP, instantiate IP, and verify the hierarchy of your design IP.
  2. 2.2
    Designing with the IP Integrator Use the Vivado IP integrator to create the uart_led subsystem.
  3. 2.3
    UltraFast Design Methodology: Design Creation Overview of the methodology guidelines covered in this course.
  4. 2.4
    Vivado Design Suite Non-Project Mode Create a design in the Vivado Design Suite non-project mode.
  5. 2.5
    Introduction to the Tcl Environment Introduces Tcl (tool command language).
  6. 2.6
    Design Analysis Using Tcl Commands Analyze a design using Tcl commands.
  7. 2.7
    Scripting in Vivado Design Suite Project Mode Explains how to write Tcl commands in the project-based flow for a design.
  8. 2.8
    Scripting in Vivado Design Suite Non-Project Mode Write Tcl commands in the non-project batch flow for a design.
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