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Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users

Release Date:
June 2018
2 days

Quick Links

Key Documentation


Existing Xilinx ISE® Design Suite FPGA designers


Optional Video


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This course will update experienced ISE software users to utilize the Vivado Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.

You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will learn about the scripting environment of the Vivado Design Suite and how to use the project-based scripting flow.

You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Software Tools

  • Vivado® System Edition 2018.1


  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Create appropriate clock and input, output delay constraints and describe timing reports that involve input and output paths
  • Analyze different timing reports
  • Define a properly constrained design
  • Describe setup and hold checks and describe the components of a timing report
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Describe all of the options available with the report_timing and report_timing_summary commands
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
  • Identify timing closure techniques using the Vivado® Design Suite
  • Describe how the UltraFast design methodology techniques work effectively through case studies and lab experiences

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Introduction to Clock Constraints Apply clock constraints and perform timing analysis.
  2. 1.2
    Generated Clocks Use the report clock networks report to determine if there are any generated clocks in a design.
  3. 1.3
    Report Clock Networks Use report clock networks to view the primary and generated clocks in a design.
  4. 1.4
    Clock Group Constraints Apply clock group constraints for asynchronous clock domains.
  5. 1.5
    I/O Constraints and Virtual Clocks Apply I/O constraints and perform timing analysis.
  6. 1.6
    Timing Constraints Wizard Use the Timing Constraints Wizard to apply missing timing constraints in a design.
  7. 1.7
    Introduction to Vivado Reports Generate and use Vivado timing reports to analyze failed timing paths.
  8. 1.8
    Setup and Hold Timing Analysis Understand setup and hold timing analysis.
  9. 1.9
    Timing Summary Report Use the post-implementation timing summary report to sign-off criteria for timing closure.
  10. 1.10
    Report Clock Interaction Use the clock interaction report to identify interactions between clock domains.
  11. 1.11
    Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing.
  12. 1.12
    Timing Constraints Priority Identify the priority of timing constraints.

Day 2

  1. 2.1
    Synchronization Circuits Use synchronization circuits for clock domain crossings.
  2. 2.2
    Report Datasheet Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  3. 2.3
    UltraFast Design Methodology: Implementation Introduces the methodology guidelines covered in this course.
  4. 2.4
    Baselining Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  5. 2.5
    Pipelining Use pipelining to improve design performance.
  6. 2.6
    I/O Timing Scenarios Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
  7. 2.7
    System-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
  8. 2.8
    Source-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
  9. 2.9
    Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning.
  10. 2.10
    Congestion Identifies congestion and addresses congestion issues.
  11. 2.11
    Physical Optimization Use physical optimization techniques for timing closure.
  12. 2.12
    UltraFast Design Methodology: Design Closure Introduces the design methodology guidelines covered in this course.
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