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Zynq SoC System Architecture

Release Date:
May 2018
Level:
Embedded Architect 3
Duration:
2 days

Quick Links

Key Documentation

Audience

System architects who are interested in architecting a system on a chip using the Zynq® SoC.

Prerequisites

  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

The Xilinx Zynq System on a Chip (SoC) provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq SoC.

This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq SoC project. It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq SoC.

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Software Tools

  • Vivado® Design or System Edition 2018.1

Hardware

  • Architecture: Zynq-7000 SoC*
  • Demo board: Zynq-7000 SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Overview Provides a general overview of the Zynq SoC.
  2. 1.2
    Application Processor Unit (APU) Explores the individual components that comprise the APU.
  3. 1.3
    Neon Co-Processor Describes the Neon co-processor that is the companion to each Cortex-A9 processor.
  4. 1.4
    Input/Output Peripherals Introduces the components that comprise the IOP block of the Zynq device PS.
  5. 1.5
    Low-Speed Peripherals: Overview Introduces the low-speed peripherals in the Zynq SoC.
  6. 1.6
    Low-Speed Peripherals: UART Introduces the UART low-speed peripheral.
  7. 1.7
    Low-Speed Peripherals: CAN Introduces the CAN low-speed peripheral.
  8. 1.8
    Low-Speed Peripherals: I2C Introduces the I2C low-speed peripheral.
  9. 1.9
    Low-Speed Peripherals: SD/SDIO Introduces the SD/SDIO low-speed peripheral.
  10. 1.10
    Low-Speed Peripherals: GPIO Introduces the GPIO low-speed peripheral.
  11. 1.11
    High-Speed Peripherals: USB Introduces the USB high-speed peripheral.
  12. 1.12
    High-Speed Peripherals: Gigabit Ethernet Introduces the Gigabit Ethernet high-speed peripheral.
  13. 1.13
    DMA Controller (DMAC) Explores the operation of the DMAC, which is located in the APU.
  14. 1.14
    DMA: Introduction and Features Introduces the direct memory access controller.
  15. 1.15
    DMA: Block Design and Interrupts Introduces the DMA block design and the DMA interrupts.
  16. 1.16
    DMA: Read and Write Introduces the concepts behind DMA reading and writing.

Day 2

  1. 2.1
    AXI: Introduction Introduces the AXI protocol.
  2. 2.2
    AXI: Variations Describes the differences and similarities among the three primary AXI variations.
  3. 2.3
    AXI: Transactions Describes different types of AXI transactions.
  4. 2.4
    PS-PL Interface Describes in detail the PS interconnect and how it affects PL architecture decisions.
  5. 2.5
    Booting Explains the boot process of the PC and configuration of the PL.
  6. 2.6
    Memory Resources Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
  7. 2.7
    Meeting Performance Goals Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques.
  8. 2.8
    Hardware Design Discusses the use and configuration of the PS in a hardware design.
  9. 2.9
    Software Design Explores the software side of the Zynq device.
  10. 2.10
    Debugging Introduces debug tools and methodology on the Zynq SoC.
  11. 2.11
    Tools and Reference Designs Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.
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