We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Zynq UltraScale+ MPSoC for the Hardware Designer

Release Date:
June 2018
Embedded Hardware 3
1 day

Quick Links

Key Documentation


Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.


  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C (to support testing of specific architectural elements)


For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers.

Course Description

This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

Software Tools

  • Vivado® Design Suite 2018.1
    • May require special Zynq UltraScale+ MPSoC family license
  • Hardware emulation environment:
    • VirtualBox
    • QEMU
    • Ubuntu desktop
    • PetaLinux


Host computer for running the above software*

* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations. This version of the class does not use a physical board, but rather a local emulation environment and the Vivado Design Suite.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic (PL)
  • Utilize QEMU to emulate hardware behavior

Course Outline

Lab Lecture Demo

Day 1

  1. 1.1
    Zynq UltraScale+ MPSoC Application Processing Unit Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.
  2. 1.2
    Zynq UltraScale+ MPSoC HW-SW Virtualization Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
  3. 1.3
    Zynq UltraScale+ MPSoC Real-Time Processing Unit Introduction to the various elements within the RPU and different modes of configuration.
  4. 1.4
    QEMU Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
  5. 1.5
    Zynq UltraScale+ MPSoC Booting How to implement the embedded system, including the boot process and boot image creation.
  6. 1.6
    First Stage Boot Loader Introduction to the FSBL, its importance, and how it can be implemented.
  7. 1.7
    Zynq UltraScale+ MPSoC Video Introduction to video, video codecs, and the Video Codec Unit available in the Zynq UltraScale MPSoC.
  8. 1.8
    Zynq UltraScale+ MPSoC System Protection Covers all the hardware elements that support the separation of software domains.
  9. 1.9
    Zynq UltraScale+ MPSoC Clocks and Resets Overview of clocking and reset, focusing more on capabilities than specific implementations.
  10. 1.10
    AXI Understanding how the PS and PL connect enables designers to create more efficient systems.
  11. 1.11
    Zynq UltraScale+ MPSoC PMU Overview of the PMU and the power-saving features of the device.
Page Bookmarked