Fundamentals of CPLD Design

Course Description

This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE® series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs. This course covers ISE features such as the Constraints Editor and PACE. Other topics include design planning, implementation options, and global timing constraints. You will ultimately configure a CPLD demo board by using Xilinx configuration software.

Level

Fundamental

Training Duration

1 day

Who Should Attend?

Digital designers interested in CPLD design who have working knowledge of basic HDL (VHDL or Verilog) and who are new to Xilinx CPLDs, ISE software, or both.

Prerequisites

• Basic HDL knowledge (VHDL or Verilog)
• Digital design experience

Software Tools

• Xilinx ISE 9.1i SP3

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe signal integrity effects
• Predict and overcome signal integrity challenges
• Simulate signal integrity effects
• Verify and derive design rules for the board design
• Apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and semiconductor circuits
• Plan your board design under FPGA-specific restrictions
• Supply the FPGAs with power
• Handle thermal aspects

Course Outline

• Course Agenda
• Introduction to Xilinx Products
• CoolRunner-II CPLD Architecture
• CPLD Software Flow
• Lab 1: Xilinx CPLD Tool Flow
• Reading CPLD Reports
• Global Constraints
• Lab 2: Constraints for CPLDs
• CPLD Software Options
• Lab 3: CPLD Implementation Options

Lab Descriptions

• Lab 1: Xilinx CPLD Tool Flow – Create a new project in the Project Navigator of the ISE software. Implement a design by using default software options and configure the CoolRunner-II CPLD demo board with iMPACT, the Xilinx In-System Programming (ISP) software.
• Lab 2: Constraints for CPLDs – Use constraints to specify clock frequencies, pin locations, and I/O standards for the CPLD demo board project. Fit the design and analyze the Timing and Fitter Reports to confirm performance and I/O placement..
• Lab 3: CPLD Implementation Options – Implement the design with default software options and evaluate the design performance versus design requirements. Apply a global timing constraint for PERIOD to the design. Change the software options and add I/O constraints to meet the design’s timing goals.

Customer Reviews 

• The instructor was friendly and very knowledgeable.
  
  
  
• I thought the course was really good. The instructor was very professional and attentive to our questions
  
  
  
• The labs were very helpful. Hands-on practice is the best way to learn, at least for me.