C-based Design: High-Level Synthesis with the Vivado HLS Tool

Course Description

The course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

Release Date

November 2015



Training Duration

2 days

Who Should Attend?

Software and hardware engineers looking to utilize high-level synthesis

  • C, C++, or System C knowledge
  • High-level synthesis for software engineers OR high-level synthesis for hardware engineers
Software Tools
  • Vivado System Edition 2015.3
  • Architecture: Zynq®-7000 All Programmable SoC and 7 series FPGAs*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board*

* This course focuses on the Zynq-7000 All Programmable SoC and 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enhance productivity by using the Vivado HLS tool
  • Describe the high-level synthesis flow
  • Use the Vivado tool HLS for a first project
  • Identify the importance of the testbench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of IP generated by the Vivado HLS tool
  • Describe how to use OpenCV functions in the Vivado HLS tool
Course Outline
Day 1
  • Introduction to High-Level Synthesis and the Vivado HLS Tool
  • Using the Vivado HLS Tool: GUI Flow
  • Demo: Vivado HLS Tool Overview
  • Lab 1: Introduction to the Vivado HLS Tool Flow
  • Vivado HLS Tool Command Line Interface
  • Lab 2: Introduction to the Vivado HLS Tool CLI Flow
  • Optimizing for Latency
  • Lab 3: The Impact of Unrolling Loops
  • Optimizing for Throughput
  • Lab 4: Optimizing for Throughput
Day 2
  • Optimizing Arrays
  • Lab 5: Handling Memories
  • Optimizing for Area
  • I/O Interfaces
  • Demo: AXI4-Streaming Interfaces
  • Lab 6: System Integration
  • HLS UltraFast Design Methodology
  • Vivado HLS Tool: C Code
  • Lab 7: Matrix Multiplication
Lab Descriptions
  • Lab 1: Introduction to the Vivado HLS Tool Flow – Utilize the GUI to simulate and create a project. Perform RTL synthesis, verification, and exporting the C design as an IP.
  • Lab 2: Introduction to the Vivado HLS Tool CLI Flow – Utilize a make file to perform C simulation. Create a project and perform C synthesis, RTL verification, and RTL packaging.
  • Lab 3: The Impact of Unrolling Loops – Analyze multiple results of the design and apply directives to optimize loop latency
  • Lab 4: Optimizing for Throughput – Optimize loop performance and modify pipelining and its affect on performance.
  • Lab 5: Handling Memories – Analyze the impact of manipulating arrays. Utilize directives to optimize the design for area.
  • Lab 6: System Integration – Set up an embedded design, create an HLS IP with the AXI Lite interface, import the IP into the embedded design, and validate the system on the demo board.
  • Lab 7: Matrix Multiplication – Write a C-code 3x3 matrix multiplier, verify the design, and apply directives to improve performance.
To Register

For class schedules as well as tuition and registration information, please contact one of our Authorized Training Providers: